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aarch64-protos.h (aarch64_ccmp_mode_to_code): New.
2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org> * config/aarch64/aarch64-protos.h (aarch64_ccmp_mode_to_code): New. * aarch64.c (aarch64_nzcv_codes): New data. (aarch64_ccmp_mode_to_code): New. (aarch64_print_operand): Output nzcv. config/aarch64/aarch64.md (cbranchcc4, *ccmp_and, *ccmp_ior, cstorecc4): New patterns. (cstore<mode>4): Handle ccmp_cc_register. * config/aarch64/predicates.md (const0_operand): New. From-SVN: r217644
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Zhenqiang Chen
Zhenqiang Chen
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3dfa7055cb
commit
cf67050334
@ -1,3 +1,14 @@
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2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>
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* config/aarch64/aarch64-protos.h (aarch64_ccmp_mode_to_code): New.
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* aarch64.c (aarch64_nzcv_codes): New data.
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(aarch64_ccmp_mode_to_code): New.
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(aarch64_print_operand): Output nzcv.
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config/aarch64/aarch64.md (cbranchcc4, *ccmp_and, *ccmp_ior, cstorecc4):
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New patterns.
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(cstore<mode>4): Handle ccmp_cc_register.
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* config/aarch64/predicates.md (const0_operand): New.
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2014-11-17 Zhenqiang Chen <zhenqiang.chen@linaro.org>
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* config/aarch64/aarch64-modes.def: Define ccmp CC mode.
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@ -314,4 +314,5 @@ extern void aarch64_final_prescan_insn (rtx_insn *);
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extern bool
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aarch64_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel);
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void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
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int aarch64_ccmp_mode_to_code (enum machine_mode mode);
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#endif /* GCC_AARCH64_PROTOS_H */
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@ -3829,6 +3829,75 @@ bit_count (unsigned HOST_WIDE_INT value)
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return count;
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}
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/* N Z C V. */
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#define AARCH64_CC_V 1
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#define AARCH64_CC_C (1 << 1)
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#define AARCH64_CC_Z (1 << 2)
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#define AARCH64_CC_N (1 << 3)
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/* N Z C V flags for ccmp. The first code is for AND op and the other
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is for IOR op. Indexed by AARCH64_COND_CODE. */
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static const int aarch64_nzcv_codes[][2] =
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{
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{AARCH64_CC_Z, 0}, /* EQ, Z == 1. */
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{0, AARCH64_CC_Z}, /* NE, Z == 0. */
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{AARCH64_CC_C, 0}, /* CS, C == 1. */
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{0, AARCH64_CC_C}, /* CC, C == 0. */
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{AARCH64_CC_N, 0}, /* MI, N == 1. */
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{0, AARCH64_CC_N}, /* PL, N == 0. */
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{AARCH64_CC_V, 0}, /* VS, V == 1. */
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{0, AARCH64_CC_V}, /* VC, V == 0. */
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{AARCH64_CC_C, 0}, /* HI, C ==1 && Z == 0. */
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{0, AARCH64_CC_C}, /* LS, !(C == 1 && Z == 0). */
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{0, AARCH64_CC_V}, /* GE, N == V. */
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{AARCH64_CC_V, 0}, /* LT, N != V. */
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{0, AARCH64_CC_Z}, /* GT, Z == 0 && N == V. */
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{AARCH64_CC_Z, 0}, /* LE, !(Z == 0 && N == V). */
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{0, 0}, /* AL, Any. */
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{0, 0}, /* NV, Any. */
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};
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int
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aarch64_ccmp_mode_to_code (enum machine_mode mode)
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{
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switch (mode)
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{
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case CC_DNEmode:
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return NE;
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case CC_DEQmode:
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return EQ;
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case CC_DLEmode:
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return LE;
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case CC_DGTmode:
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return GT;
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case CC_DLTmode:
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return LT;
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case CC_DGEmode:
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return GE;
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case CC_DLEUmode:
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return LEU;
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case CC_DGTUmode:
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return GTU;
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case CC_DLTUmode:
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return LTU;
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case CC_DGEUmode:
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return GEU;
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default:
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gcc_unreachable ();
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}
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}
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void
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aarch64_print_operand (FILE *f, rtx x, char code)
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{
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@ -4193,6 +4262,40 @@ aarch64_print_operand (FILE *f, rtx x, char code)
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output_addr_const (asm_out_file, x);
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break;
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case 'K':
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{
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int cond_code;
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/* Print nzcv. */
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if (!COMPARISON_P (x))
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{
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output_operand_lossage ("invalid operand for '%%%c'", code);
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return;
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}
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cond_code = aarch64_get_condition_code_1 (CCmode, GET_CODE (x));
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gcc_assert (cond_code >= 0);
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asm_fprintf (f, "%d", aarch64_nzcv_codes[cond_code][0]);
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}
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break;
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case 'k':
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{
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int cond_code;
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/* Print nzcv. */
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if (!COMPARISON_P (x))
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{
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output_operand_lossage ("invalid operand for '%%%c'", code);
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return;
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}
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cond_code = aarch64_get_condition_code_1 (CCmode, GET_CODE (x));
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gcc_assert (cond_code >= 0);
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asm_fprintf (f, "%d", aarch64_nzcv_codes[cond_code][1]);
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}
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break;
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default:
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output_operand_lossage ("invalid operand prefix '%%%c'", code);
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return;
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@ -246,6 +246,54 @@
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"
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)
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(define_expand "cbranchcc4"
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[(set (pc) (if_then_else
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(match_operator 0 "aarch64_comparison_operator"
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[(match_operand 1 "cc_register" "")
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(match_operand 2 "const0_operand")])
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(label_ref (match_operand 3 "" ""))
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(pc)))]
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""
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"")
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(define_insn "*ccmp_and"
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[(set (match_operand 1 "ccmp_cc_register" "")
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(compare
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(and:SI
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(match_operator 4 "aarch64_comparison_operator"
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[(match_operand 0 "ccmp_cc_register" "")
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(const_int 0)])
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(match_operator 5 "aarch64_comparison_operator"
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[(match_operand:GPI 2 "register_operand" "r,r,r")
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(match_operand:GPI 3 "aarch64_ccmp_operand" "r,Uss,Usn")]))
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(const_int 0)))]
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"aarch64_ccmp_mode_to_code (GET_MODE (operands[1])) == GET_CODE (operands[5])"
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"@
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ccmp\\t%<w>2, %<w>3, %k5, %m4
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ccmp\\t%<w>2, %<w>3, %k5, %m4
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ccmn\\t%<w>2, #%n3, %k5, %m4"
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[(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
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)
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(define_insn "*ccmp_ior"
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[(set (match_operand 1 "ccmp_cc_register" "")
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(compare
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(ior:SI
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(match_operator 4 "aarch64_comparison_operator"
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[(match_operand 0 "ccmp_cc_register" "")
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(const_int 0)])
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(match_operator 5 "aarch64_comparison_operator"
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[(match_operand:GPI 2 "register_operand" "r,r,r")
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(match_operand:GPI 3 "aarch64_ccmp_operand" "r,Uss,Usn")]))
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(const_int 0)))]
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"aarch64_ccmp_mode_to_code (GET_MODE (operands[1])) == GET_CODE (operands[5])"
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"@
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ccmp\\t%<w>2, %<w>3, %K5, %M4
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ccmp\\t%<w>2, %<w>3, %K5, %M4
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ccmn\\t%<w>2, #%n3, %K5, %M4"
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[(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
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)
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(define_insn "*condjump"
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[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
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[(match_operand 1 "cc_register" "") (const_int 0)])
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@ -2419,6 +2467,18 @@
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"
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)
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(define_expand "cstorecc4"
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[(set (match_operand:SI 0 "register_operand")
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(match_operator 1 "aarch64_comparison_operator"
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[(match_operand 2 "ccmp_cc_register")
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(match_operand 3 "const0_operand")]))]
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""
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"{
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emit_insn (gen_rtx_SET (SImode, operands[0], operands[1]));
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DONE;
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}")
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(define_expand "cstore<mode>4"
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[(set (match_operand:SI 0 "register_operand" "")
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(match_operator:SI 1 "aarch64_comparison_operator"
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@ -2567,15 +2627,19 @@
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(match_operand:ALLI 3 "register_operand" "")))]
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""
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{
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rtx ccreg;
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enum rtx_code code = GET_CODE (operands[1]);
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if (code == UNEQ || code == LTGT)
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FAIL;
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ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
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XEXP (operands[1], 1));
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operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
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if (!ccmp_cc_register (XEXP (operands[1], 0),
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GET_MODE (XEXP (operands[1], 0))))
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{
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rtx ccreg;
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ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
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XEXP (operands[1], 1));
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operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
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}
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}
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)
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@ -30,6 +30,11 @@
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(ior (match_code "symbol_ref")
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(match_operand 0 "register_operand")))
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;; Return true if OP a (const_int 0) operand.
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(define_predicate "const0_operand"
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(and (match_code "const_int, const_double")
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(match_test "op == CONST0_RTX (mode)")))
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(define_predicate "aarch64_ccmp_immediate"
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(and (match_code "const_int")
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(match_test "IN_RANGE (INTVAL (op), -31, 31)")))
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