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alpha.md (DWI): New mode attribute.
* config/alpha/alpha.md (DWI): New mode attribute. (*sadd<modesuffix>): Macroize insn from *saddl and *saddq using I48MODE mode iterator. (addv<mode>3): Macroize insn from addvsi3 and addvdi3 using I48MODE mode iterator. (neg<mode>2): Macroize insn from negsi2 and negdi2 using I48MODE mode iterator. (negv<mode>2): Macroize insn from negvsi2 and negvdi2 using I48MODE mode iterator. (sub<mode>3): Macroize insn from subsi3 and subdi3 using I48MODE mode iterator. (*ssub<modesuffix>): Macroize insn from *ssubl and *ssubq using I48MODE mode iterator. (subv<mode>3): Macroize insn from subvsi3 and subvdi3 using I48MODE mode iterator. (mul<mode>3): Macroize insn from mulsi3 and muldi3 using I48MODE mode iterator. (mulv<mode>3): Macroize insn from mulvsi3 and mulvdi3 using I48MODE mode iterator. (*iornot<mode>3): Macroize insn from *iornotsi3 and *iornotdi3 using I48MODE mode iterator. (*xornot<mode>3): Macroize insn from *xornotsi3 and *xornotdi3 using I48MODE mode iterator. From-SVN: r192370
This commit is contained in:
Uros Bizjak
parent
21a092a900
commit
cf1e4683aa
@ -1,3 +1,29 @@
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2012-10-11 Uros Bizjak <ubizjak@gmail.com>
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* config/alpha/alpha.md (DWI): New mode attribute.
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(*sadd<modesuffix>): Macroize insn from *saddl and *saddq using
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I48MODE mode iterator.
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(addv<mode>3): Macroize insn from addvsi3 and addvdi3 using
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I48MODE mode iterator.
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(neg<mode>2): Macroize insn from negsi2 and negdi2 using
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I48MODE mode iterator.
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(negv<mode>2): Macroize insn from negvsi2 and negvdi2 using
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I48MODE mode iterator.
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(sub<mode>3): Macroize insn from subsi3 and subdi3 using
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I48MODE mode iterator.
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(*ssub<modesuffix>): Macroize insn from *ssubl and *ssubq using
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I48MODE mode iterator.
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(subv<mode>3): Macroize insn from subvsi3 and subvdi3 using
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I48MODE mode iterator.
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(mul<mode>3): Macroize insn from mulsi3 and muldi3 using
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I48MODE mode iterator.
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(mulv<mode>3): Macroize insn from mulvsi3 and mulvdi3 using
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I48MODE mode iterator.
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(*iornot<mode>3): Macroize insn from *iornotsi3 and *iornotdi3 using
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I48MODE mode iterator.
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(*xornot<mode>3): Macroize insn from *xornotsi3 and *xornotdi3 using
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I48MODE mode iterator.
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2012-10-11 Jason Merrill <jason@redhat.com>
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* configure.ac (gcc_cv_as_aix_ref): Fix typo.
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@ -97,8 +123,7 @@
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2012-10-10 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.h (PRINT_OPERAND_PUNCT_VALID_P):
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Delete '.'.
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* config/rs6000/rs6000.h (PRINT_OPERAND_PUNCT_VALID_P): Delete '.'.
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2012-10-10 Jakub Jelinek <jakub@redhat.com>
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@ -118,8 +143,7 @@
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(lto_write_tree): Adjust.
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(output_eh_region): Likewise.
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(output_struct_function_base): Likewise.
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* lto-streamer.c (lto_streamer_hooks_init): Initialize location
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hooks.
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* lto-streamer.c (lto_streamer_hooks_init): Initialize location hooks.
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* lto-streamer.h (lto_input_location): Adjust prototype.
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(lto_output_location): Likewise.
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* streamer-hooks.h (struct streamer_hooks): Adjust prototype
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@ -200,8 +224,7 @@
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(rs6000_print_options_internal): New function for expanded
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-mdebug=reg option printing to print both the ISA options, and the
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builtins that are enabled.
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(rs6000_print_isa_options): New function to print the ISA
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options.
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(rs6000_print_isa_options): New function to print the ISA options.
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(rs6000_print_builtin_options): New function to print the builtin
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functions enabled.
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@ -240,7 +263,7 @@
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2012-10-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* config.gcc: Enable zEC12 for with-arch and with-tune
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configure switches.
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configure switches.
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* common/config/s390/s390-common.c (processor_flags_table): Add
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zEC12 entry.
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* config/s390/2827.md: New file.
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@ -253,8 +276,7 @@
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Set parameter defaults for zEC12.
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(legitimate_reload_fp_constant_p): Adjust comment.
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(preferred_la_operand_p): Adjust comment.
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(s390_expand_insv): Generate insv pattern without CC clobber for
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zEC12.
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(s390_expand_insv): Generate insv pattern without CC clobber for zEC12.
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(s390_adjust_priority): Add zEC12 check.
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(s390_issue_rate): Return 2 for zEC12.
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(s390_reorg): Enable code optimizations for zEC12.
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@ -282,8 +304,10 @@
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(*movsf_insn): Likewise.
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(*movdf_insn_sp64): Likewise.
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(*mov<VM32:mode>_insn): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
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(*mov<VM64:mode>_insn_sp64): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
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(*mov<VM64:mode>_insn_sp32): Likewise, use 'fsrc2s' instead of 'fsrc1s'.
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(*mov<VM64:mode>_insn_sp64): Likewise, use 'fsrc2s'
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instead of 'fsrc1s'.
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(*mov<VM64:mode>_insn_sp32): Likewise, use 'fsrc2s'
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instead of 'fsrc1s'.
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(VIS logical instructions): Mark as visl.
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(pdist_vis): Use 'pdist'.
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(pditsn<mode>_vis): Use 'pdistn'.
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@ -314,15 +338,16 @@
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* Makefile.in (fold-const.o): Add depencence on hash-table.h.
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(dse.o): Likewise.
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(cfg.o): Likewise.
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* fold-const.c (fold_checksum_tree): Change to new type-safe hash table.
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* fold-const.c (fold_checksum_tree): Change to new
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type-safe hash table.
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* (print_fold_checksum): Likewise.
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* cfg.c (var bb_original): Likewise.
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* (var bb_copy): Likewise.
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* (var loop_copy): Likewise.
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* hash-table.h (template hash_table): Constify parameters for find...
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and remove_elt... member functions.
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(hash_table::empty) Correct size expression.
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(hash_table::clear_slot) Correct deleted entry assignment.
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(hash_table::empty) Correct size expression.
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(hash_table::clear_slot) Correct deleted entry assignment.
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* dse.c (var rtx_group_table): Change to new type-safe hash table.
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2012-10-09 Steven Bosscher <steven@gcc.gnu.org>
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@ -92,6 +92,7 @@
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;; Other mode iterators
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(define_mode_iterator I12MODE [QI HI])
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(define_mode_iterator I48MODE [SI DI])
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(define_mode_attr DWI [(SI "DI") (DI "TI")])
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(define_mode_attr modesuffix [(SI "l") (DI "q")])
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;; Where necessary, the suffixes _le and _be are used to distinguish between
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@ -358,20 +359,6 @@
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operands[7] = gen_lowpart (SImode, operands[5]);
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})
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(define_insn "addvsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
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(match_operand:SI 2 "sext_add_operand" "rI,O")))
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(trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
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(sign_extend:DI (match_dup 2)))
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(sign_extend:DI (plus:SI (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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""
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"@
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addlv %r1,%2,%0
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sublv %r1,%n2,%0")
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(define_expand "adddi3"
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[(set (match_operand:DI 0 "register_operand" "")
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(plus:DI (match_operand:DI 1 "register_operand" "")
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@ -522,15 +509,16 @@
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FAIL;
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})
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(define_insn "*saddl"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
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(match_operand:SI 2 "const48_operand" "I,I"))
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(match_operand:SI 3 "sext_add_operand" "rI,O")))]
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(define_insn "*sadd<modesuffix>"
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[(set (match_operand:I48MODE 0 "register_operand" "=r,r")
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(plus:I48MODE
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(mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r")
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(match_operand:I48MODE 2 "const48_operand" "I,I"))
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(match_operand:I48MODE 3 "sext_add_operand" "rI,O")))]
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""
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"@
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s%2addl %1,%3,%0
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s%2subl %1,%n3,%0")
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s%2add<modesuffix> %1,%3,%0
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s%2sub<modesuffix> %1,%n3,%0")
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(define_insn "*saddl_se"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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@ -563,35 +551,25 @@
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operands[8] = gen_lowpart (SImode, operands[6]);
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})
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(define_insn "*saddq"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
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(match_operand:DI 2 "const48_operand" "I,I"))
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(match_operand:DI 3 "sext_add_operand" "rI,O")))]
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""
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"@
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s%2addq %1,%3,%0
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s%2subq %1,%n3,%0")
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(define_insn "addvdi3"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
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(match_operand:DI 2 "sext_add_operand" "rI,O")))
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(trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
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(sign_extend:TI (match_dup 2)))
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(sign_extend:TI (plus:DI (match_dup 1)
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(match_dup 2))))
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(define_insn "addv<mode>3"
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[(set (match_operand:I48MODE 0 "register_operand" "=r,r")
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(plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ")
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(match_operand:I48MODE 2 "sext_add_operand" "rI,O")))
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(trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1))
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(sign_extend:<DWI> (match_dup 2)))
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(sign_extend:<DWI> (plus:I48MODE (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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""
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"@
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addqv %r1,%2,%0
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subqv %r1,%n2,%0")
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add<modesuffix>v %r1,%2,%0
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sub<modesuffix>v %r1,%n2,%0")
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(define_insn "negsi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
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(define_insn "neg<mode>2"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))]
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""
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"subl $31,%1,%0")
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"sub<modesuffix> $31,%1,%0")
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(define_insn "*negsi_se"
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[(set (match_operand:DI 0 "register_operand" "=r")
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@ -600,36 +578,21 @@
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""
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"subl $31,%1,%0")
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(define_insn "negvsi2"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(neg:SI (match_operand:SI 1 "register_operand" "r")))
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(trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
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(sign_extend:DI (neg:SI (match_dup 1))))
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(define_insn "negv<mode>2"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r")))
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(trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1)))
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(sign_extend:<DWI> (neg:I48MODE (match_dup 1))))
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(const_int 0))]
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""
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"sublv $31,%1,%0")
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"sub<modesuffix>v $31,%1,%0")
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(define_insn "negdi2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
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(define_insn "sub<mode>3"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
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(match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))]
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""
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"subq $31,%1,%0")
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(define_insn "negvdi2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(neg:DI (match_operand:DI 1 "register_operand" "r")))
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(trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
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(sign_extend:TI (neg:DI (match_dup 1))))
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(const_int 0))]
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""
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"subqv $31,%1,%0")
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(define_insn "subsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
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(match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
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""
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"subl %r1,%2,%0")
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"sub<modesuffix> %r1,%2,%0")
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(define_insn "*subsi_se"
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[(set (match_operand:DI 0 "register_operand" "=r")
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@ -647,32 +610,14 @@
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""
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"subl %r1,%2,%0")
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(define_insn "subvsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
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(match_operand:SI 2 "reg_or_8bit_operand" "rI")))
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(trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
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(sign_extend:DI (match_dup 2)))
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(sign_extend:DI (minus:SI (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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(define_insn "*ssub<modesuffix>"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(minus:I48MODE
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(mult:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r")
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(match_operand:I48MODE 2 "const48_operand" "I"))
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(match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))]
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""
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"sublv %r1,%2,%0")
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(define_insn "subdi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
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(match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
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""
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"subq %r1,%2,%0")
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(define_insn "*ssubl"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
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(match_operand:SI 2 "const48_operand" "I"))
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(match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
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""
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"s%2subl %1,%3,%0")
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"s%2sub<modesuffix> %1,%3,%0")
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(define_insn "*ssubl_se"
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[(set (match_operand:DI 0 "register_operand" "=r")
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@ -683,34 +628,26 @@
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""
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"s%2subl %1,%3,%0")
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(define_insn "*ssubq"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
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(match_operand:DI 2 "const48_operand" "I"))
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(match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
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""
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"s%2subq %1,%3,%0")
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(define_insn "subvdi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
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(match_operand:DI 2 "reg_or_8bit_operand" "rI")))
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(trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
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(sign_extend:TI (match_dup 2)))
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(sign_extend:TI (minus:DI (match_dup 1)
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(match_dup 2))))
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(define_insn "subv<mode>3"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ")
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(match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))
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(trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1))
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(sign_extend:<DWI> (match_dup 2)))
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(sign_extend:<DWI> (minus:I48MODE (match_dup 1)
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(match_dup 2))))
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(const_int 0))]
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""
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"subqv %r1,%2,%0")
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"sub<modesuffix>v %r1,%2,%0")
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(define_insn "mulsi3"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
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(match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
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(define_insn "mul<mode>3"
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[(set (match_operand:I48MODE 0 "register_operand" "=r")
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(mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ")
|
||||
(match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))]
|
||||
""
|
||||
"mull %r1,%2,%0"
|
||||
"mul<modesuffix> %r1,%2,%0"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "opsize" "si")])
|
||||
(set_attr "opsize" "<mode>")])
|
||||
|
||||
(define_insn "*mulsi_se"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
@ -722,40 +659,19 @@
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "opsize" "si")])
|
||||
|
||||
(define_insn "mulvsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
|
||||
(match_operand:SI 2 "reg_or_8bit_operand" "rI")))
|
||||
(trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
|
||||
(sign_extend:DI (match_dup 2)))
|
||||
(sign_extend:DI (mult:SI (match_dup 1)
|
||||
(match_dup 2))))
|
||||
(define_insn "mulv<mode>3"
|
||||
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
||||
(mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ")
|
||||
(match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))
|
||||
(trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1))
|
||||
(sign_extend:<DWI> (match_dup 2)))
|
||||
(sign_extend:<DWI> (mult:I48MODE (match_dup 1)
|
||||
(match_dup 2))))
|
||||
(const_int 0))]
|
||||
""
|
||||
"mullv %r1,%2,%0"
|
||||
"mul<modesuffix>v %r1,%2,%0"
|
||||
[(set_attr "type" "imul")
|
||||
(set_attr "opsize" "si")])
|
||||
|
||||
(define_insn "muldi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
|
||||
""
|
||||
"mulq %r1,%2,%0"
|
||||
[(set_attr "type" "imul")])
|
||||
|
||||
(define_insn "mulvdi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
|
||||
(match_operand:DI 2 "reg_or_8bit_operand" "rI")))
|
||||
(trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
|
||||
(sign_extend:TI (match_dup 2)))
|
||||
(sign_extend:TI (mult:DI (match_dup 1)
|
||||
(match_dup 2))))
|
||||
(const_int 0))]
|
||||
""
|
||||
"mulqv %r1,%2,%0"
|
||||
[(set_attr "type" "imul")])
|
||||
(set_attr "opsize" "<mode>")])
|
||||
|
||||
(define_expand "umuldi3_highpart"
|
||||
[(set (match_operand:DI 0 "register_operand" "")
|
||||
@ -1222,18 +1138,11 @@
|
||||
"ornot $31,%1,%0"
|
||||
[(set_attr "type" "ilog")])
|
||||
|
||||
(define_insn "*iornotsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(ior:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
|
||||
(match_operand:SI 2 "reg_or_0_operand" "rJ")))]
|
||||
""
|
||||
"ornot %r2,%1,%0"
|
||||
[(set_attr "type" "ilog")])
|
||||
|
||||
(define_insn "*iornotdi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
|
||||
(match_operand:DI 2 "reg_or_0_operand" "rJ")))]
|
||||
(define_insn "*iornot<mode>3"
|
||||
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
||||
(ior:I48MODE (not:I48MODE
|
||||
(match_operand:I48MODE 1 "reg_or_8bit_operand" "rI"))
|
||||
(match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))]
|
||||
""
|
||||
"ornot %r2,%1,%0"
|
||||
[(set_attr "type" "ilog")])
|
||||
@ -1258,18 +1167,11 @@
|
||||
eqv %r1,%N2,%0"
|
||||
[(set_attr "type" "ilog")])
|
||||
|
||||
(define_insn "*xornotsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(not:SI (xor:SI (match_operand:SI 1 "register_operand" "%rJ")
|
||||
(match_operand:SI 2 "register_operand" "rI"))))]
|
||||
""
|
||||
"eqv %r1,%2,%0"
|
||||
[(set_attr "type" "ilog")])
|
||||
|
||||
(define_insn "*xornotdi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
|
||||
(not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
|
||||
(match_operand:DI 2 "register_operand" "rI"))))]
|
||||
(define_insn "*xornot<mode>3"
|
||||
[(set (match_operand:I48MODE 0 "register_operand" "=r")
|
||||
(not:I48MODE (xor:I48MODE
|
||||
(match_operand:I48MODE 1 "register_operand" "%rJ")
|
||||
(match_operand:I48MODE 2 "register_operand" "rI"))))]
|
||||
""
|
||||
"eqv %r1,%2,%0"
|
||||
[(set_attr "type" "ilog")])
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user