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i386.md (*cmpi<FPCMP:unord><MODEF:mode>_mixed): Merge with *cmpi<FPCMP:unord><MODEF:mode>_sse using enabled attribute.
* config/i386/i386.md (*cmpi<FPCMP:unord><MODEF:mode>_mixed): Merge with *cmpi<FPCMP:unord><MODEF:mode>_sse using enabled attribute. (*extendsfdf2_mixed): Merge with *extendsfdf2_sse using enabled attribute. (*truncdfsf_fast_mixed): Merge with *truncdfsf_fast_sse using enabled attribute. (*float<SWI48:mode><MODEF:mode>2_mixed): Rename from *float<SWI48:mode><MODEF:mode>2_sse. (*absneg<mode>2_mixed): Merge with *absneg<mode>2_sse using enabled attribute. (*fop_<mode>_comm_mixed): Merge with *fop_<mode>_comm_sse using enabled attribute. From-SVN: r222131
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
20e38fcf4f
commit
cf0ed95b57
@ -1,3 +1,18 @@
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2015-04-15 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (*cmpi<FPCMP:unord><MODEF:mode>_mixed):
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Merge with *cmpi<FPCMP:unord><MODEF:mode>_sse using enabled attribute.
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(*extendsfdf2_mixed): Merge with *extendsfdf2_sse using enabled
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attribute.
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(*truncdfsf_fast_mixed): Merge with *truncdfsf_fast_sse using
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enabled attribute.
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(*float<SWI48:mode><MODEF:mode>2_mixed): Rename from
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*float<SWI48:mode><MODEF:mode>2_sse.
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(*absneg<mode>2_mixed): Merge with *absneg<mode>2_sse using
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enabled attribute.
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(*fop_<mode>_comm_mixed): Merge with *fop_<mode>_comm_sse using
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enabled attribute.
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2015-04-15 Tom de Vries <tom@codesourcery.com>
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PR other/65487
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@ -1641,19 +1641,15 @@
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(compare:FPCMP
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(match_operand:MODEF 0 "register_operand" "f,x")
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(match_operand:MODEF 1 "nonimmediate_operand" "f,xm")))]
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"TARGET_MIX_SSE_I387
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&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode)"
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"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"
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"* return output_fp_compare (insn, operands, true,
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<FPCMP:MODE>mode == CCFPUmode);"
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[(set_attr "type" "fcmp,ssecomi")
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(set_attr "prefix" "orig,maybe_vex")
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(set_attr "mode" "<MODEF:MODE>")
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(set (attr "prefix_rep")
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(if_then_else (eq_attr "type" "ssecomi")
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(const_string "0")
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(const_string "*")))
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(set_attr "prefix_rep" "*,0")
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(set (attr "prefix_data16")
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(cond [(eq_attr "type" "fcmp")
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(cond [(eq_attr "alternative" "0")
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(const_string "*")
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(eq_attr "mode" "DF")
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(const_string "1")
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@ -1661,28 +1657,12 @@
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(const_string "0")))
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(set_attr "athlon_decode" "vector")
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(set_attr "amdfam10_decode" "direct")
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(set_attr "bdver1_decode" "double")])
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(define_insn "*cmpi<FPCMP:unord><MODEF:mode>_sse"
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[(set (reg:FPCMP FLAGS_REG)
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(compare:FPCMP
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(match_operand:MODEF 0 "register_operand" "x")
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(match_operand:MODEF 1 "nonimmediate_operand" "xm")))]
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"TARGET_SSE_MATH
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&& SSE_FLOAT_MODE_P (<MODEF:MODE>mode)"
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"* return output_fp_compare (insn, operands, true,
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<FPCMP:MODE>mode == CCFPUmode);"
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[(set_attr "type" "ssecomi")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "<MODEF:MODE>")
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(set_attr "prefix_rep" "0")
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(set (attr "prefix_data16")
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(if_then_else (eq_attr "mode" "DF")
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(const_string "1")
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(const_string "0")))
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(set_attr "athlon_decode" "vector")
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(set_attr "amdfam10_decode" "direct")
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(set_attr "bdver1_decode" "double")])
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(set_attr "bdver1_decode" "double")
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(set (attr "enabled")
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(cond [(eq_attr "alternative" "0")
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(symbol_ref "TARGET_MIX_SSE_I387")
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]
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(symbol_ref "true")))])
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(define_insn "*cmpi<FPCMP:unord><X87MODEF:mode>_i387"
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[(set (reg:FPCMP FLAGS_REG)
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@ -4051,7 +4031,7 @@
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,m,x")
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(float_extend:DF
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(match_operand:SF 1 "nonimmediate_operand" "fm,f,xm")))]
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"TARGET_SSE2 && TARGET_MIX_SSE_I387"
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"TARGET_SSE2 && TARGET_SSE_MATH"
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{
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switch (which_alternative)
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{
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@ -4068,16 +4048,12 @@
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}
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[(set_attr "type" "fmov,fmov,ssecvt")
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(set_attr "prefix" "orig,orig,maybe_vex")
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(set_attr "mode" "SF,XF,DF")])
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(define_insn "*extendsfdf2_sse"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=x")
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(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
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"TARGET_SSE2 && TARGET_SSE_MATH"
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"%vcvtss2sd\t{%1, %d0|%d0, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "DF")])
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(set_attr "mode" "SF,XF,DF")
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(set (attr "enabled")
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(cond [(eq_attr "alternative" "0,1")
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(symbol_ref "TARGET_MIX_SSE_I387")
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]
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(symbol_ref "true")))])
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(define_insn "*extendsfdf2_i387"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,m")
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@ -4205,11 +4181,13 @@
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(float_truncate:SF (match_operand:DF 1)))
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(clobber (match_operand:SF 2))])])
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;; SSE alternative doesn't depend on flag_unsafe_math_optimizations,
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;; because nothing we do there is unsafe.
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(define_insn "*truncdfsf_fast_mixed"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=fm,x")
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(float_truncate:SF
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(match_operand:DF 1 "nonimmediate_operand" "f ,xm")))]
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"TARGET_SSE2 && TARGET_MIX_SSE_I387 && flag_unsafe_math_optimizations"
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"TARGET_SSE2 && TARGET_SSE_MATH"
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{
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switch (which_alternative)
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{
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@ -4223,19 +4201,13 @@
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}
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[(set_attr "type" "fmov,ssecvt")
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(set_attr "prefix" "orig,maybe_vex")
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(set_attr "mode" "SF")])
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;; Yes, this one doesn't depend on flag_unsafe_math_optimizations,
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;; because nothing we do here is unsafe.
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(define_insn "*truncdfsf_fast_sse"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=x")
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(float_truncate:SF
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(match_operand:DF 1 "nonimmediate_operand" "xm")))]
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"TARGET_SSE2 && TARGET_SSE_MATH"
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"%vcvtsd2ss\t{%1, %d0|%d0, %1}"
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[(set_attr "type" "ssecvt")
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(set_attr "prefix" "maybe_vex")
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(set_attr "mode" "SF")])
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(set_attr "mode" "SF")
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(set (attr "enabled")
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(cond [(eq_attr "alternative" "0")
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(symbol_ref "TARGET_MIX_SSE_I387
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&& flag_unsafe_math_optimizations")
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]
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(symbol_ref "true")))])
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(define_insn "*truncdfsf_fast_i387"
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[(set (match_operand:SF 0 "nonimmediate_operand" "=fm")
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@ -4863,7 +4835,7 @@
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}
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})
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(define_insn "*float<SWI48:mode><MODEF:mode>2_sse"
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(define_insn "*float<SWI48:mode><MODEF:mode>2_mixed"
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[(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
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(float:MODEF
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(match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))]
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@ -8836,17 +8808,13 @@
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[(match_operand:MODEF 1 "register_operand" "0,x,0,0")]))
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(use (match_operand:<ssevecmode> 2 "nonimmediate_operand" "xm,0,X,X"))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (<MODE>mode)"
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"#")
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(define_insn "*absneg<mode>2_sse"
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[(set (match_operand:MODEF 0 "register_operand" "=x,x,!r")
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(match_operator:MODEF 3 "absneg_operator"
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[(match_operand:MODEF 1 "register_operand" "0 ,x,0")]))
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(use (match_operand:<ssevecmode> 2 "register_operand" "xm,0,X"))
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(clobber (reg:CC FLAGS_REG))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
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"#")
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"#"
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[(set (attr "enabled")
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(cond [(eq_attr "alternative" "2")
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(symbol_ref "TARGET_MIX_SSE_I387")
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]
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(symbol_ref "true")))])
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(define_insn "*absneg<mode>2_i387"
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[(set (match_operand:X87MODEF 0 "register_operand" "=f,!r")
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@ -13594,11 +13562,11 @@
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;; so use special patterns for add and mull.
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(define_insn "*fop_<mode>_comm_mixed"
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[(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
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[(set (match_operand:MODEF 0 "register_operand" "=f,x,v")
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(match_operator:MODEF 3 "binary_fp_operator"
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[(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,x")
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(match_operand:MODEF 2 "nonimmediate_operand" "fm,xm,xm")]))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_MIX_SSE_I387
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[(match_operand:MODEF 1 "nonimmediate_operand" "%0,0,v")
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(match_operand:MODEF 2 "nonimmediate_operand" "fm,xm,vm")]))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& COMMUTATIVE_ARITH_P (operands[3])
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&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"* return output_387_binary_op (insn, operands);"
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@ -13612,24 +13580,12 @@
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(const_string "fop"))))
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(set_attr "isa" "*,noavx,avx")
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(set_attr "prefix" "orig,orig,vex")
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(set_attr "mode" "<MODE>")])
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(define_insn "*fop_<mode>_comm_sse"
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[(set (match_operand:MODEF 0 "register_operand" "=x,v")
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(match_operator:MODEF 3 "binary_fp_operator"
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[(match_operand:MODEF 1 "nonimmediate_operand" "%0,v")
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(match_operand:MODEF 2 "nonimmediate_operand" "xm,vm")]))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH
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&& COMMUTATIVE_ARITH_P (operands[3])
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&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"* return output_387_binary_op (insn, operands);"
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[(set (attr "type")
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(if_then_else (match_operand:MODEF 3 "mult_operator")
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(const_string "ssemul")
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(const_string "sseadd")))
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(set_attr "isa" "noavx,avx")
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<MODE>")])
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(set_attr "mode" "<MODE>")
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(set (attr "enabled")
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(cond [(eq_attr "alternative" "0")
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(symbol_ref "TARGET_MIX_SSE_I387")
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]
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(const_string "*")))])
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(define_insn "*fop_<mode>_comm_i387"
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[(set (match_operand:MODEF 0 "register_operand" "=f")
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