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git://gcc.gnu.org/git/gcc.git
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IBM Z: vec_store_len_r/vec_load_len_r fix
This fixes a problem with the vec_store_len_r intrinsic. The macros
mapping the intrinsic to a GCC builtin had the wrong signature.
With the patch an immediate length operand of vlrl/vstrl is handled
the same way as if it was passed in a register to vlrlr/vstrlr.
Values bigger than 15 always load the full vector. If it can be
recognized that it is in effect a full vector register load or store
it is now implemented with vl/vst instead.
gcc/ChangeLog:
2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/constraints.md ("j>f", "jb4"): New constraints.
* config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix
macro definitions.
* config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a
separate expander.
("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst.
Change constraint for vlrl/vstrl to jb4.
gcc/testsuite/ChangeLog:
2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
* gcc.target/s390/zvector/vec_load_len_r.c: New test.
* gcc.target/s390/zvector/vec_store_len_r.c: New test.
This commit is contained in:
Andreas Krebbel
parent
2786c0221b
commit
cd5fa73359
@ -1,3 +1,13 @@
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2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
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* config/s390/constraints.md ("j>f", "jb4"): New constraints.
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* config/s390/vecintrin.h (vec_load_len_r, vec_store_len_r): Fix
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macro definitions.
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* config/s390/vx-builtins.md ("vlrlrv16qi", "vstrlrv16qi"): Add a
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separate expander.
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("*vlrlrv16qi", "*vstrlrv16qi"): Add alternative for vl/vst.
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Change constraint for vlrl/vstrl to jb4.
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2020-04-30 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
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* var-tracking.c (vt_initialize): Move variables pre and post
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@ -38,6 +38,8 @@
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;; matching K constraint
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;; jm6: An integer operand with the lowest order 6 bits all ones.
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;; jdd: A constant operand that fits into the data section.
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;; j>f: An integer operand whose lower 32 bits are greater than or equal to 15
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;; jb4: An unsigned constant 4 bit operand.
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;; t -- Access registers 36 and 37.
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;; v -- Vector registers v0-v31.
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;; C -- A signed 8-bit constant (-128..127)
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@ -425,7 +427,7 @@
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;;
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;; Vector constraints follow.
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;; Vector and scalar constraints for constant values follow.
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;;
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(define_constraint "j00"
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@ -462,6 +464,16 @@
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"@internal An integer operand with the lowest order 6 bits all ones."
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(match_operand 0 "const_int_6bitset_operand"))
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(define_constraint "j>f"
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"@internal An integer operand whose lower 32 bits are greater than or equal to 15."
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(and (match_code "const_int")
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(match_test "(unsigned int)(ival & 0xffffffff) >= 15")))
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(define_constraint "jb4"
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"@internal Constant unsigned integer 4 bit value"
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(and (match_code "const_int")
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(match_test "ival >= 0 && ival <= 15")))
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;;
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;; Memory constraints follow.
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;;
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@ -111,8 +111,10 @@ __lcbb(const void *ptr, int bndry)
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#define vec_round(X) __builtin_s390_vfi((X), 4, 4)
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#define vec_doublee(X) __builtin_s390_vfll((X))
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#define vec_floate(X) __builtin_s390_vflr((X), 0, 0)
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#define vec_load_len_r(X,Y) __builtin_s390_vlrl((Y),(X))
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#define vec_store_len_r(X,Y) __builtin_s390_vstrl((Y),(X))
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#define vec_load_len_r(X,L) \
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(__vector unsigned char)__builtin_s390_vlrlr((L),(X))
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#define vec_store_len_r(X,Y,L) \
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__builtin_s390_vstrlr((__vector signed char)(X),(L),(Y))
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#define vec_all_nan(a) \
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__extension__ ({ \
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@ -202,16 +202,34 @@
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"vlbb\t%v0,%1,%2"
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[(set_attr "op_type" "VRX")])
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(define_insn "vlrlrv16qi"
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[(set (match_operand:V16QI 0 "register_operand" "=v,v")
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(unspec:V16QI [(match_operand:BLK 2 "memory_operand" "Q,Q")
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(match_operand:SI 1 "nonmemory_operand" "d,C")]
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; Vector load rightmost with length
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(define_expand "vlrlrv16qi"
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[(set (match_operand:V16QI 0 "register_operand" "")
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(unspec:V16QI [(match_operand:BLK 2 "memory_operand" "")
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(match_operand:SI 1 "nonmemory_operand" "")]
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UNSPEC_VEC_LOAD_LEN_R))]
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"TARGET_VXE"
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{
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/* vlrlr sets all length values beyond 15 to 15. Emulate the same
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behavior for immediate length operands. vlrl would trigger a
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SIGILL for too large immediate operands. */
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if (CONST_INT_P (operands[1])
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&& (UINTVAL (operands[1]) & 0xffffffff) > 15)
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operands[1] = GEN_INT (15);
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})
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(define_insn "*vlrlrv16qi"
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[(set (match_operand:V16QI 0 "register_operand" "=v, v, v")
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(unspec:V16QI [(match_operand:BLK 2 "memory_operand" "Q, R, Q")
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(match_operand:SI 1 "nonmemory_operand" "d,j>f,jb4")]
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UNSPEC_VEC_LOAD_LEN_R))]
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"TARGET_VXE"
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"@
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vlrlr\t%v0,%1,%2
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vl\t%v0,%2%A2
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vlrl\t%v0,%2,%1"
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[(set_attr "op_type" "VRS,VSI")])
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[(set_attr "op_type" "VRS,VRX,VSI")])
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; FIXME: The following two patterns might using vec_merge. But what is
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@ -545,16 +563,32 @@
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; Vector store rightmost with length
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(define_insn "vstrlrv16qi"
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[(set (match_operand:BLK 2 "memory_operand" "=Q,Q")
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(unspec:BLK [(match_operand:V16QI 0 "register_operand" "v,v")
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(match_operand:SI 1 "nonmemory_operand" "d,C")]
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(define_expand "vstrlrv16qi"
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[(set (match_operand:BLK 2 "memory_operand" "")
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(unspec:BLK [(match_operand:V16QI 0 "register_operand" "")
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(match_operand:SI 1 "nonmemory_operand" "")]
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UNSPEC_VEC_STORE_LEN_R))]
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"TARGET_VXE"
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{
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/* vstrlr sets all length values beyond 15 to 15. Emulate the same
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behavior for immediate length operands. vstrl would trigger a
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SIGILL for too large immediate operands. */
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if (CONST_INT_P (operands[1])
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&& (UINTVAL (operands[1]) & 0xffffffff) > 15)
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operands[1] = GEN_INT (15);
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})
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(define_insn "*vstrlrv16qi"
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[(set (match_operand:BLK 2 "memory_operand" "=Q, R, Q")
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(unspec:BLK [(match_operand:V16QI 0 "register_operand" "v, v, v")
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(match_operand:SI 1 "nonmemory_operand" "d,j>f,jb4")]
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UNSPEC_VEC_STORE_LEN_R))]
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"TARGET_VXE"
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"@
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vstrlr\t%v0,%2,%1
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vstrl\t%v0,%1,%2"
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[(set_attr "op_type" "VRS,VSI")])
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vstrlr\t%v0,%1,%2
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vst\t%v0,%2%A2
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vstrl\t%v0,%2,%1"
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[(set_attr "op_type" "VRS,VRX,VSI")])
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@ -1,3 +1,8 @@
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2020-04-30 Andreas Krebbel <krebbel@linux.ibm.com>
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* gcc.target/s390/zvector/vec_load_len_r.c: New test.
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* gcc.target/s390/zvector/vec_store_len_r.c: New test.
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2020-04-29 Jakub Jelinek <jakub@redhat.com>
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PR target/94704
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94
gcc/testsuite/gcc.target/s390/zvector/vec_load_len_r.c
Normal file
94
gcc/testsuite/gcc.target/s390/zvector/vec_load_len_r.c
Normal file
@ -0,0 +1,94 @@
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/* { dg-do run } */
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/* { dg-require-effective-target s390_vxe2 } */
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/* { dg-options "-O3 -mzarch -march=arch13 -mzvector --save-temps" } */
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#include <string.h>
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#include <vecintrin.h>
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typedef vector unsigned char uv16qi;
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const unsigned char test_vec[16] = { 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 };
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#define NUM_TEST_LENGTHS 3
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unsigned int test_len[NUM_TEST_LENGTHS] = { 0, 12, 18 };
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/* Proceeding from left to right, the specified number (LEN+1) of
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bytes from SOURCE are stored right-justified in TARGET. */
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void __attribute__((noinline, noclone, target ("arch=zEC12")))
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emul (const unsigned char *source, unsigned char *target, unsigned int len)
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{
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int start = 15 - len;
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if (start < 0)
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start = 0;
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for (int s = 0, t = start; t < 16; s++, t++)
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target[t] = source[s];
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}
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uv16qi __attribute__((noinline, noclone))
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vec_load_len_r_reg (const unsigned char *s, unsigned int len)
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{
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return vec_load_len_r (s, len);
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}
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void __attribute__((noinline, noclone))
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vec_load_len_r_mem (const unsigned char *s, uv16qi *t, unsigned int *len)
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{
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*t = vec_load_len_r (s, *len);
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}
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#define GEN_CONST_FUNC(CONST) \
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static uv16qi inline \
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vec_load_len_r_const##CONST (const unsigned char *s) \
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{ \
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return vec_load_len_r (s, CONST); \
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}
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#define GEN_CONST_TEST(CONST) \
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memset (exp_result, 0, 16); \
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emul (test_vec, exp_result, CONST); \
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result = (uv16qi) { 0 }; \
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result = vec_load_len_r_const##CONST (test_vec); \
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if (memcmp ((char*)&result, exp_result, 16) != 0) \
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__builtin_abort ();
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GEN_CONST_FUNC(0)
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GEN_CONST_FUNC(12)
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GEN_CONST_FUNC(18)
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int
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main ()
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{
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unsigned char exp_result[16];
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uv16qi result;
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for (int i = 0; i < NUM_TEST_LENGTHS; i++)
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{
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memset (exp_result, 0, 16);
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emul (test_vec, exp_result, test_len[i]);
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result = (uv16qi) { 0 };
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result = vec_load_len_r_reg (test_vec, test_len[i]);
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if (memcmp ((char*)&result, exp_result, 16) != 0)
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__builtin_abort ();
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result = (uv16qi) { 0 };
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vec_load_len_r_mem (test_vec, &result, &test_len[i]);
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if (memcmp ((char*)&result, exp_result, 16) != 0)
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__builtin_abort ();
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}
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GEN_CONST_TEST(0)
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GEN_CONST_TEST(12)
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GEN_CONST_TEST(18)
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return 0;
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}
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/* vec_load_len_r_reg and vec_load_len_r_mem */
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/* { dg-final { scan-assembler-times "vlrlr\t" 2 } } */
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/* For the 2 constants. The 3. should be implemented with vl. */
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/* { dg-final { scan-assembler-times "vlrl\t" 2 } } */
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94
gcc/testsuite/gcc.target/s390/zvector/vec_store_len_r.c
Normal file
94
gcc/testsuite/gcc.target/s390/zvector/vec_store_len_r.c
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@ -0,0 +1,94 @@
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/* { dg-do run } */
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/* { dg-require-effective-target s390_vxe2 } */
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/* { dg-options "-O3 -mzarch -march=arch13 -mzvector --save-temps" } */
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#include <string.h>
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#include <vecintrin.h>
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typedef vector unsigned char uv16qi;
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uv16qi test_vec = (uv16qi){ 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 };
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#define NUM_TEST_LENGTHS 3
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unsigned int test_len[NUM_TEST_LENGTHS] = { 0, 12, 18 };
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/* Proceeding from left to right, the specified number (LEN+1) of
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rightmost bytes from SOURCE are stored in TARGET. */
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void __attribute__((noinline, noclone, target ("arch=zEC12")))
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emul (unsigned char *source, unsigned char *target, unsigned int len)
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{
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int start = 15 - len;
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if (start < 0)
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start = 0;
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for (int s = start, t = 0; s < 16; s++, t++)
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target[t] = source[s];
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}
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void __attribute__((noinline, noclone))
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vec_store_len_r_reg (uv16qi s, unsigned char *t, unsigned int len)
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{
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vec_store_len_r (s, t, len);
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}
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void __attribute__((noinline, noclone))
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vec_store_len_r_mem (uv16qi *s, unsigned char *t, unsigned int *len)
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{
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vec_store_len_r (*s, t, *len);
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}
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#define GEN_CONST_FUNC(CONST) \
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static void inline \
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vec_store_len_r_const##CONST (uv16qi s, unsigned char *t) \
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{ \
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vec_store_len_r (s, t, CONST); \
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}
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#define GEN_CONST_TEST(CONST) \
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memset (exp_result, 0, 16); \
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emul ((unsigned char*)&test_vec, exp_result, CONST); \
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memset (result, 0, 16); \
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vec_store_len_r_const##CONST (test_vec, result); \
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if (memcmp (result, exp_result, 16) != 0) \
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__builtin_abort ();
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GEN_CONST_FUNC(0)
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GEN_CONST_FUNC(12)
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GEN_CONST_FUNC(18)
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int
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main ()
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{
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unsigned char exp_result[16];
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unsigned char result[16];
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for (int i = 0; i < NUM_TEST_LENGTHS; i++)
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{
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memset (exp_result, 0, 16);
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emul ((unsigned char*)&test_vec, exp_result, test_len[i]);
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memset (result, 0, 16);
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vec_store_len_r_reg (test_vec, result, test_len[i]);
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if (memcmp (result, exp_result, 16) != 0)
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__builtin_abort ();
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memset (result, 0, 16);
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vec_store_len_r_mem (&test_vec, result, &test_len[i]);
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if (memcmp (result, exp_result, 16) != 0)
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__builtin_abort ();
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}
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GEN_CONST_TEST(0)
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GEN_CONST_TEST(12)
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GEN_CONST_TEST(18)
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return 0;
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}
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/* vec_store_len_r_reg and vec_store_len_r_mem */
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/* { dg-final { scan-assembler-times "vstrlr\t" 2 } } */
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/* For the 2 constants. The 3. should be implemented with vst. */
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/* { dg-final { scan-assembler-times "vstrl\t" 2 } } */
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