diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4eccac89594a..1491f6ecd077 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2006-07-13  Adrian Strae˝tling  <straetling@de.ibm.com>
+
+	* config/s390/s390.md: ("cmpstrsi", "*cmpstr<mode>"): New
+	pattern.
+	("strlen<mode>", "*strlen<mode>"): Use hard reg 0 in SImode.
+
 2005-07-13  Eric Christopher  <echristo@redhat.com>
 
 	* config/mips/mips.c (mips_canonicalize_comparison): New.
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 92555c49b845..6aaed96e9708 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -1761,12 +1761,12 @@
 ;
 
 (define_expand "strlen<mode>"
-  [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
+  [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" ""))
    (parallel
     [(set (match_dup 4)
 	  (unspec:P [(const_int 0)
 		      (match_operand:BLK 1 "memory_operand" "")
-		      (reg:QI 0)
+		      (reg:SI 0)
 		      (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
      (clobber (scratch:P))
      (clobber (reg:CC CC_REGNUM))])
@@ -1786,7 +1786,7 @@
   [(set (match_operand:P 0 "register_operand" "=a")
 	(unspec:P [(match_operand:P 2 "general_operand" "0")
 		    (mem:BLK (match_operand:P 3 "register_operand" "1"))
-		    (reg:QI 0)
+		    (reg:SI 0)
 		    (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
    (clobber (match_scratch:P 1 "=a"))
    (clobber (reg:CC CC_REGNUM))]
@@ -1795,6 +1795,52 @@
   [(set_attr "length" "8")
    (set_attr "type" "vs")])
 
+;
+; cmpstrM instruction pattern(s).
+;
+
+(define_expand "cmpstrsi"
+  [(set (reg:SI 0) (const_int 0))
+   (parallel
+    [(clobber (match_operand 3 "" ""))
+     (clobber (match_dup 4))
+     (set (reg:CCU CC_REGNUM)
+	  (compare:CCU (match_operand:BLK 1 "memory_operand" "")
+	 	       (match_operand:BLK 2 "memory_operand" "")))
+     (use (reg:SI 0))])
+   (parallel
+    [(set (match_operand:SI 0 "register_operand" "=d")
+	  (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT))
+     (clobber (reg:CC CC_REGNUM))])]
+  ""
+{
+  /* As the result of CMPINT is inverted compared to what we need,
+     we have to swap the operands.  */
+  rtx op1 = operands[2];
+  rtx op2 = operands[1];
+  rtx addr1 = gen_reg_rtx (Pmode);
+  rtx addr2 = gen_reg_rtx (Pmode);
+
+  emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
+  emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX));
+  operands[1] = replace_equiv_address_nv (op1, addr1);
+  operands[2] = replace_equiv_address_nv (op2, addr2);
+  operands[3] = addr1;
+  operands[4] = addr2;
+})
+
+(define_insn "*cmpstr<mode>"
+  [(clobber (match_operand:P 0 "register_operand" "=d"))
+   (clobber (match_operand:P 1 "register_operand" "=d"))
+   (set (reg:CCU CC_REGNUM)
+	(compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0"))
+		     (mem:BLK (match_operand:P 3 "register_operand" "1"))))
+   (use (reg:SI 0))]
+  ""
+  "clst\t%0,%1\;jo\t.-4"
+  [(set_attr "length" "8")
+   (set_attr "type" "vs")])
+ 
 ;
 ; movmemM instruction pattern(s).
 ;