mirror of
git://gcc.gnu.org/git/gcc.git
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cpuid.h (__cpuid_count): New defines.
* config/i386/cpuid.h (__cpuid_count): New defines. * config/i386/driver-i386.c (struct cache_desc): New structure. (describe_cache): Use struct cache_desc to pass cache descriptions. (detect_l2_cache): Ditto. Rename from decode_l2_cache. (detect_caches_amd): Use struct cache_desc to describe caches. (decode_caches_intel): Use struct cache_desc to pass cache descriptions. Update descriptions to match latest (rev -032, December 2007) CPUID documentation. Do not check valid bit here. Check for Xeon MP value 0x49 problems. (detect_caches_cpuid2): New function, split from detect_caches_intel. Check valid bit before calling decode_caches_intel. Detect number of times to repeat CPUID instruction. (detect_caches_cpuid4): New function. (detect_caches_intel): Depending on max_level, call detect_caches_cpuid2 or detect_caches_cpuid4. Call detect_l2_cache only when other methods fail to provide valid L2 cache description. From-SVN: r141064
This commit is contained in:
Uros Bizjak
parent
e40375e0e2
commit
cb0dee885c
@ -1,3 +1,23 @@
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2008-10-11 Uros Bizjak <ubizjak@gmail.com>
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Andi Kleen <ak@linux.intel.com>
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* config/i386/cpuid.h (__cpuid_count): New defines.
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* config/i386/driver-i386.c (struct cache_desc): New structure.
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(describe_cache): Use struct cache_desc to pass cache descriptions.
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(detect_l2_cache): Ditto. Rename from decode_l2_cache.
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(detect_caches_amd): Use struct cache_desc to describe caches.
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(decode_caches_intel): Use struct cache_desc to pass cache
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descriptions. Update descriptions to match latest (rev -032,
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December 2007) CPUID documentation. Do not check valid bit here.
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Check for Xeon MP value 0x49 problems.
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(detect_caches_cpuid2): New function, split from detect_caches_intel.
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Check valid bit before calling decode_caches_intel. Detect number
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of times to repeat CPUID instruction.
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(detect_caches_cpuid4): New function.
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(detect_caches_intel): Depending on max_level, call
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detect_caches_cpuid2 or detect_caches_cpuid4. Call detect_l2_cache
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only when other methods fail to provide valid L2 cache description.
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2008-10-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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PR middle-end/37608
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@ -13,10 +33,10 @@
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2008-10-11 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/rs6000.md (aux_truncdfsf2): Remove TARGET_SINGLE_FLOAT.
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(addsf3, subsf3, mulsf3 ! TARGET_POWERPC): Remove TARGET_SINGLE_FLOAT
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and fp_type.
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(divdf3): Reformat long line.
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* config/rs6000/rs6000.md (aux_truncdfsf2): Remove TARGET_SINGLE_FLOAT.
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(addsf3, subsf3, mulsf3 ! TARGET_POWERPC): Remove TARGET_SINGLE_FLOAT
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and fp_type.
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(divdf3): Reformat long line.
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2008-10-11 Michael J. Eager <eager@eagercon.com>
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@ -25,8 +45,7 @@
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(rs6000_handle_option): Process -mfpu options.
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* config/rs6000/rs6000.h: (TARGET_XILINX_FPU): New.
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(enum fpu_type_t): New.
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* config/rs6000/rs6000.md (attr fp_type): New.
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Include xfpu.md.
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* config/rs6000/rs6000.md (attr fp_type): New. Include xfpu.md.
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(addsf3, subsf3, mulsf3, adddf3, subdf3, muldf3, trunctfdf2): Set
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fp_type.
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(floatsisf2): Remove TARGET_SINGLE_FPU condition.
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@ -74,6 +74,13 @@
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"xchg{l}\t{%%}ebx, %1\n\t" \
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: "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \
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"cpuid\n\t" \
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"xchg{l}\t{%%}ebx, %1\n\t" \
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: "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#else
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/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
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nor alternatives in i386 code. */
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@ -83,12 +90,24 @@
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"xchgl\t%%ebx, %1\n\t" \
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: "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("xchgl\t%%ebx, %1\n\t" \
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"cpuid\n\t" \
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"xchgl\t%%ebx, %1\n\t" \
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: "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#endif
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#else
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("cpuid\n\t" \
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: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#define __cpuid_count(level, count, a, b, c, d) \
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__asm__ ("cpuid\n\t" \
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: "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
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: "0" (level), "2" (count))
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#endif
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/* Return highest supported input value for cpuid instruction. ext can
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@ -1,5 +1,5 @@
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/* Subroutines for the gcc driver.
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Copyright (C) 2006, 2007 Free Software Foundation, Inc.
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Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
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This file is part of GCC.
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@ -28,34 +28,45 @@ const char *host_detect_local_cpu (int argc, const char **argv);
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#ifdef __GNUC__
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#include "cpuid.h"
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/* Returns parameters that describe L1_ASSOC associative cache of size
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L1_SIZEKB with lines of size L1_LINE. */
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struct cache_desc
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{
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unsigned sizekb;
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unsigned assoc;
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unsigned line;
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};
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/* Returns command line parameters that describe size and
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cache line size of the processor caches. */
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static char *
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describe_cache (unsigned l1_sizekb, unsigned l1_line,
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unsigned l1_assoc ATTRIBUTE_UNUSED, unsigned l2_sizekb)
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describe_cache (struct cache_desc level1, struct cache_desc level2)
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{
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char size[100], line[100], size2[100];
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/* At the moment, gcc middle-end does not use the information about the
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associativity of the cache. */
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/* At the moment, gcc does not use the information
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about the associativity of the cache. */
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sprintf (size, "--param l1-cache-size=%u", l1_sizekb);
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sprintf (line, "--param l1-cache-line-size=%u", l1_line);
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sprintf (size2, "--param l2-cache-size=%u", l2_sizekb);
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sprintf (size, "--param l1-cache-size=%u", level1.sizekb);
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sprintf (line, "--param l1-cache-line-size=%u", level1.line);
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sprintf (size2, "--param l2-cache-size=%u", level2.sizekb);
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return concat (size, " ", line, " ", size2, " ", NULL);
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}
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/* Detect L2 cache parameters using CPUID extended function 0x80000006. */
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static void
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decode_l2_cache (unsigned *l2_size, unsigned *l2_line, unsigned *l2_assoc)
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detect_l2_cache (struct cache_desc *level2)
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{
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unsigned eax, ebx, ecx, edx, assoc;
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unsigned eax, ebx, ecx, edx;
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unsigned assoc;
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__cpuid (0x80000006, eax, ebx, ecx, edx);
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*l2_size = (ecx >> 16) & 0xffff;
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*l2_line = ecx & 0xff;
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level2->sizekb = (ecx >> 16) & 0xffff;
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level2->line = ecx & 0xff;
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assoc = (ecx >> 12) & 0xf;
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if (assoc == 6)
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assoc = 8;
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@ -65,7 +76,8 @@ decode_l2_cache (unsigned *l2_size, unsigned *l2_line, unsigned *l2_assoc)
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assoc = 32 + (assoc - 0xa) * 16;
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else if (assoc >= 0xd && assoc <= 0xe)
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assoc = 96 + (assoc - 0xd) * 32;
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*l2_assoc = assoc;
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level2->assoc = assoc;
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}
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/* Returns the description of caches for an AMD processor. */
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@ -74,243 +86,261 @@ static const char *
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detect_caches_amd (unsigned max_ext_level)
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{
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unsigned eax, ebx, ecx, edx;
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unsigned l1_sizekb, l1_line, l1_assoc;
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unsigned l2_sizekb = 0, l2_line = 0, l2_assoc = 0;
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struct cache_desc level1, level2 = {0, 0, 0};
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if (max_ext_level < 0x80000005)
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return "";
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__cpuid (0x80000005, eax, ebx, ecx, edx);
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l1_line = ecx & 0xff;
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l1_sizekb = (ecx >> 24) & 0xff;
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l1_assoc = (ecx >> 16) & 0xff;
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level1.sizekb = (ecx >> 24) & 0xff;
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level1.assoc = (ecx >> 16) & 0xff;
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level1.line = ecx & 0xff;
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if (max_ext_level >= 0x80000006)
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decode_l2_cache (&l2_sizekb, &l2_line, &l2_assoc);
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detect_l2_cache (&level2);
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return describe_cache (l1_sizekb, l1_line, l1_assoc, l2_sizekb);
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return describe_cache (level1, level2);
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}
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/* Stores the size of the L1/2 cache and cache line, and the associativity
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of the cache according to REG to L1_SIZEKB, L1_LINE, L1_ASSOC and
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L2_SIZEKB. */
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/* Decodes the size, the associativity and the cache line size of
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L1/L2 caches of an Intel processor. Values are based on
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"Intel Processor Identification and the CPUID Instruction"
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[Application Note 485], revision -032, December 2007. */
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static void
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decode_caches_intel (unsigned reg, unsigned *l1_sizekb, unsigned *l1_line,
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unsigned *l1_assoc, unsigned *l2_sizekb,
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unsigned *l2_line, unsigned *l2_assoc)
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decode_caches_intel (unsigned reg, bool xeon_mp,
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struct cache_desc *level1, struct cache_desc *level2)
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{
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unsigned i, val;
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int i;
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if (((reg >> 31) & 1) != 0)
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return;
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for (i = 24; i >= 0; i -= 8)
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switch ((reg >> i) & 0xff)
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{
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case 0x0a:
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level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
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break;
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case 0x0c:
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level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
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break;
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case 0x2c:
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level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
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break;
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case 0x39:
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level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
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break;
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case 0x3a:
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level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
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break;
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case 0x3b:
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level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
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break;
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case 0x3c:
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level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
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break;
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case 0x3d:
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level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
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break;
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case 0x3e:
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level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
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break;
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case 0x41:
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level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
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break;
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case 0x42:
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level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
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break;
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case 0x43:
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level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
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break;
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case 0x44:
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level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
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break;
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case 0x45:
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level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
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break;
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case 0x49:
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if (xeon_mp)
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break;
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level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
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break;
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case 0x4e:
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level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
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break;
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case 0x60:
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level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
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break;
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case 0x66:
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level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
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break;
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case 0x67:
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level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
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break;
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case 0x68:
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level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
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break;
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case 0x78:
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level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
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break;
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case 0x79:
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level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
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break;
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case 0x7a:
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level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
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break;
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case 0x7b:
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level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
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break;
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case 0x7c:
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level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
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break;
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case 0x7d:
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level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
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break;
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case 0x7f:
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level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
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break;
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case 0x82:
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level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
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break;
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case 0x83:
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level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
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break;
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case 0x84:
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level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
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break;
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case 0x85:
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level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
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break;
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case 0x86:
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level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
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break;
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case 0x87:
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level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
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for (i = 0; i < 4; i++)
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default:
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break;
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}
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}
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/* Detect cache parameters using CPUID function 2. */
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static void
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detect_caches_cpuid2 (bool xeon_mp,
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struct cache_desc *level1, struct cache_desc *level2)
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{
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unsigned eax, ebx, ecx, edx;
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int nreps;
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__cpuid (2, eax, ebx, ecx, edx);
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nreps = eax & 0x0f;
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eax &= ~0x0f;
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while (--nreps >= 0)
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{
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val = reg & 0xff;
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reg >>= 8;
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if (!((eax >> 31) & 1))
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decode_caches_intel (eax, xeon_mp, level1, level2);
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if (!((ebx >> 31) & 1))
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decode_caches_intel (ebx, xeon_mp, level1, level2);
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if (!((ecx >> 31) & 1))
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decode_caches_intel (ecx, xeon_mp, level1, level2);
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if (!((edx >> 31) & 1))
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decode_caches_intel (edx, xeon_mp, level1, level2);
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switch (val)
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if (nreps)
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__cpuid (2, eax, ebx, ecx, edx);
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}
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}
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/* Detect cache parameters using CPUID function 4. This
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method doesn't require hardcoded tables. */
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enum cache_type
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{
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CACHE_END = 0,
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CACHE_DATA = 1,
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CACHE_INST = 2,
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CACHE_UNIFIED = 3
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};
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static void
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detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2)
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{
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struct cache_desc *cache;
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unsigned eax, ebx, ecx, edx;
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int count;
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for (count = 0;; count++)
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{
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__cpuid_count(4, count, eax, ebx, ecx, edx);
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switch (eax & 0x1f)
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{
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case 0xa:
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*l1_sizekb = 8;
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*l1_line = 32;
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*l1_assoc = 2;
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break;
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case 0xc:
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*l1_sizekb = 16;
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*l1_line = 32;
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*l1_assoc = 4;
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break;
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case 0x2c:
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*l1_sizekb = 32;
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*l1_line = 64;
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*l1_assoc = 8;
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break;
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case 0x39:
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*l2_sizekb = 128;
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*l2_line = 64;
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*l2_assoc = 4;
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break;
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case 0x3a:
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*l2_sizekb = 192;
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*l2_line = 64;
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*l2_assoc = 6;
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break;
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case 0x3b:
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*l2_sizekb = 128;
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*l2_line = 64;
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*l2_assoc = 2;
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break;
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||||
case 0x3c:
|
||||
*l2_sizekb = 256;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 4;
|
||||
break;
|
||||
case 0x3d:
|
||||
*l2_sizekb = 384;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 6;
|
||||
break;
|
||||
case 0x3e:
|
||||
*l2_sizekb = 512;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 4;
|
||||
break;
|
||||
case 0x41:
|
||||
*l2_sizekb = 128;
|
||||
*l2_line = 32;
|
||||
*l2_assoc = 4;
|
||||
break;
|
||||
case 0x42:
|
||||
*l2_sizekb = 256;
|
||||
*l2_line = 32;
|
||||
*l2_assoc = 4;
|
||||
break;
|
||||
case 0x43:
|
||||
*l2_sizekb = 512;
|
||||
*l2_line = 32;
|
||||
*l2_assoc = 4;
|
||||
break;
|
||||
case 0x44:
|
||||
*l2_sizekb = 1024;
|
||||
*l2_line = 32;
|
||||
*l2_assoc = 4;
|
||||
break;
|
||||
case 0x45:
|
||||
*l2_sizekb = 2048;
|
||||
*l2_line = 32;
|
||||
*l2_assoc = 4;
|
||||
break;
|
||||
case 0x49:
|
||||
*l2_sizekb = 4096;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 16;
|
||||
break;
|
||||
case 0x60:
|
||||
*l1_sizekb = 16;
|
||||
*l1_line = 64;
|
||||
*l1_assoc = 8;
|
||||
break;
|
||||
case 0x66:
|
||||
*l1_sizekb = 8;
|
||||
*l1_line = 64;
|
||||
*l1_assoc = 4;
|
||||
break;
|
||||
case 0x67:
|
||||
*l1_sizekb = 16;
|
||||
*l1_line = 64;
|
||||
*l1_assoc = 4;
|
||||
break;
|
||||
case 0x68:
|
||||
*l1_sizekb = 32;
|
||||
*l1_line = 64;
|
||||
*l1_assoc = 4;
|
||||
break;
|
||||
case 0x78:
|
||||
*l2_sizekb = 1024;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 4;
|
||||
break;
|
||||
case 0x79:
|
||||
*l2_sizekb = 128;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case 0x7a:
|
||||
*l2_sizekb = 256;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case 0x7b:
|
||||
*l2_sizekb = 512;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case 0x7c:
|
||||
*l2_sizekb = 1024;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case 0x7d:
|
||||
*l2_sizekb = 2048;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case 0x7f:
|
||||
*l2_sizekb = 512;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 2;
|
||||
break;
|
||||
case 0x82:
|
||||
*l2_sizekb = 256;
|
||||
*l2_line = 32;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case 0x83:
|
||||
*l2_sizekb = 512;
|
||||
*l2_line = 32;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case 0x84:
|
||||
*l2_sizekb = 1024;
|
||||
*l2_line = 32;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case 0x85:
|
||||
*l2_sizekb = 2048;
|
||||
*l2_line = 32;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case 0x86:
|
||||
*l2_sizekb = 512;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 4;
|
||||
break;
|
||||
case 0x87:
|
||||
*l2_sizekb = 1024;
|
||||
*l2_line = 64;
|
||||
*l2_assoc = 8;
|
||||
break;
|
||||
case CACHE_END:
|
||||
return;
|
||||
case CACHE_DATA:
|
||||
case CACHE_UNIFIED:
|
||||
{
|
||||
switch ((eax >> 5) & 0x07)
|
||||
{
|
||||
case 1:
|
||||
cache = level1;
|
||||
break;
|
||||
case 2:
|
||||
cache = level2;
|
||||
break;
|
||||
default:
|
||||
cache = NULL;
|
||||
}
|
||||
|
||||
if (cache)
|
||||
{
|
||||
unsigned sets = ecx + 1;
|
||||
unsigned part;
|
||||
|
||||
cache->line = (ebx & 0x0fff) + 1;
|
||||
ebx >>= 12;
|
||||
|
||||
part = (ebx & 0x03ff) + 1;
|
||||
ebx >>= 10;
|
||||
|
||||
cache->assoc = (ebx & 0x03ff) + 1;
|
||||
|
||||
cache->sizekb = (cache->assoc * part
|
||||
* cache->line * sets) / 1024;
|
||||
}
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Returns the description of caches for an intel processor. */
|
||||
/* Returns the description of caches for an Intel processor. */
|
||||
|
||||
static const char *
|
||||
detect_caches_intel (unsigned max_level, unsigned max_ext_level)
|
||||
detect_caches_intel (bool xeon_mp, unsigned max_level, unsigned max_ext_level)
|
||||
{
|
||||
unsigned eax, ebx, ecx, edx;
|
||||
unsigned l1_sizekb = 0, l1_line = 0, assoc = 0;
|
||||
unsigned l2_sizekb = 0, l2_line = 0, l2_assoc = 0;
|
||||
struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0};
|
||||
|
||||
if (max_level < 2)
|
||||
if (max_level >= 4)
|
||||
detect_caches_cpuid4 (&level1, &level2);
|
||||
else if (max_level >= 2)
|
||||
detect_caches_cpuid2 (xeon_mp, &level1, &level2);
|
||||
else
|
||||
return "";
|
||||
|
||||
__cpuid (2, eax, ebx, ecx, edx);
|
||||
|
||||
decode_caches_intel (eax, &l1_sizekb, &l1_line, &assoc,
|
||||
&l2_sizekb, &l2_line, &l2_assoc);
|
||||
decode_caches_intel (ebx, &l1_sizekb, &l1_line, &assoc,
|
||||
&l2_sizekb, &l2_line, &l2_assoc);
|
||||
decode_caches_intel (ecx, &l1_sizekb, &l1_line, &assoc,
|
||||
&l2_sizekb, &l2_line, &l2_assoc);
|
||||
decode_caches_intel (edx, &l1_sizekb, &l1_line, &assoc,
|
||||
&l2_sizekb, &l2_line, &l2_assoc);
|
||||
|
||||
if (!l1_sizekb)
|
||||
if (level1.sizekb == 0)
|
||||
return "";
|
||||
|
||||
/* Newer Intel CPUs are equipped with AMD style L2 cache info */
|
||||
if (max_ext_level >= 0x80000006)
|
||||
decode_l2_cache (&l2_sizekb, &l2_line, &l2_assoc);
|
||||
/* Intel CPUs are equipped with AMD style L2 cache info. Try this
|
||||
method if other methods fail to provide L2 cache parameters. */
|
||||
if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
|
||||
detect_l2_cache (&level2);
|
||||
|
||||
return describe_cache (l1_sizekb, l1_line, assoc, l2_sizekb);
|
||||
return describe_cache (level1, level2);
|
||||
}
|
||||
|
||||
/* This will be called by the spec parser in gcc.c when it sees
|
||||
@ -334,11 +364,12 @@ const char *host_detect_local_cpu (int argc, const char **argv)
|
||||
const char *cache = "";
|
||||
const char *options = "";
|
||||
|
||||
unsigned int eax, ebx, ecx, edx;
|
||||
unsigned int eax, ebx, ecx, edx;
|
||||
|
||||
unsigned int max_level, ext_level;
|
||||
|
||||
unsigned int vendor;
|
||||
unsigned int family;
|
||||
unsigned int model, family;
|
||||
|
||||
unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
|
||||
unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
|
||||
@ -364,6 +395,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
|
||||
__cpuid (1, eax, ebx, ecx, edx);
|
||||
|
||||
/* We don't care for extended family. */
|
||||
model = (eax >> 4) & 0x0f;
|
||||
family = (eax >> 8) & 0x0f;
|
||||
|
||||
has_sse3 = ecx & bit_SSE3;
|
||||
@ -396,7 +428,10 @@ const char *host_detect_local_cpu (int argc, const char **argv)
|
||||
if (vendor == *(const unsigned int*) "Auth")
|
||||
cache = detect_caches_amd (ext_level);
|
||||
else if (vendor == *(const unsigned int*) "Genu")
|
||||
cache = detect_caches_intel (max_level, ext_level);
|
||||
{
|
||||
bool xeon_mp = (family == 15 && model == 6);
|
||||
cache = detect_caches_intel (xeon_mp, max_level, ext_level);
|
||||
}
|
||||
}
|
||||
|
||||
if (vendor == *(const unsigned int*) "Auth")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user