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expmed.c (extract_fixed_bit_field): Remove unused code.

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* expmed.c (extract_fixed_bit_field): Remove unused code.
	* system.h: Poison SLOW_ZERO_EXTEND.
	* doc/tm.texi: Remove.
	* config/1750a/1750a.h (SLOW_ZERO_EXTEND): Remove.
	* config/arm/arm.h: Likewise.
	* config/avr/avr.h: Likewise.
	* config/clipper/clipper.h: Likewise.
	* config/convex/convex.h: Likewise.
	* config/d30v/d30v.h: Likewise.
	* config/dsp16xx/dsp16xx.h: Likewise.
	* config/elxsi/elxsi.h: Likewise.
	* config/fr30/fr30.h: Likewise.
	* config/h8300/h8300.h: Likewise.
	* config/i370/i370.h: Likewise.
	* config/i386/i386.h: Likewise.
	* config/m68k/m68k.h: Likewise.
	* config/mips/mips.h: Likewise.
	* config/ns32k/ns32k.h: Likewise.
	* config/pdp11/pdp11.h: Likewise.
	* config/pj/pj.h: Likewise.
	* config/s390/s390.h: Likewise.
	* config/sh/sh.h: Likewise.
	* config/stormy16/stormy16.h: Likewise.
	* config/v850/v850.h: Likewise.
	* config/vax/vax.h: Likewise.
	* config/we32k/we32k.h: Likewise.

From-SVN: r48893
This commit is contained in:
Kazu Hirata 2002-01-16 02:37:37 +00:00 committed by Kazu Hirata
parent bed9a20d55
commit c99d986a71
27 changed files with 32 additions and 147 deletions
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29
gcc/ChangeLog
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@ -1,3 +1,32 @@
2002-01-15 Kazu Hirata <kazu@hxi.com>
* expmed.c (extract_fixed_bit_field): Remove unused code.
* system.h: Poison SLOW_ZERO_EXTEND.
* doc/tm.texi: Remove.
* config/1750a/1750a.h (SLOW_ZERO_EXTEND): Remove.
* config/arm/arm.h: Likewise.
* config/avr/avr.h: Likewise.
* config/clipper/clipper.h: Likewise.
* config/convex/convex.h: Likewise.
* config/d30v/d30v.h: Likewise.
* config/dsp16xx/dsp16xx.h: Likewise.
* config/elxsi/elxsi.h: Likewise.
* config/fr30/fr30.h: Likewise.
* config/h8300/h8300.h: Likewise.
* config/i370/i370.h: Likewise.
* config/i386/i386.h: Likewise.
* config/m68k/m68k.h: Likewise.
* config/mips/mips.h: Likewise.
* config/ns32k/ns32k.h: Likewise.
* config/pdp11/pdp11.h: Likewise.
* config/pj/pj.h: Likewise.
* config/s390/s390.h: Likewise.
* config/sh/sh.h: Likewise.
* config/stormy16/stormy16.h: Likewise.
* config/v850/v850.h: Likewise.
* config/vax/vax.h: Likewise.
* config/we32k/we32k.h: Likewise.
2002-01-15 Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/rs6000.md (altivec_stvx): Add parallels to stvx.

3
gcc/config/1750a/1750a.h
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@ -770,9 +770,6 @@ enum reg_class { NO_REGS, R2, R0_1, INDEX_REGS, BASE_REGS, ALL_REGS, LIM_REG_CLA
move-instruction pairs, we will do a movstr or libcall instead. */
#define MOVE_RATIO 4
/* Define this if zero-extension is slow (more than one real instruction). */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0

5
gcc/config/arm/arm.h
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@ -2385,11 +2385,6 @@ typedef struct
((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
: ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
/* Define this if zero-extension is slow (more than one real instruction).
On the ARM, it is more than one instruction only if not fetching from
memory. */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0

12
gcc/config/avr/avr.h
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@ -1797,18 +1797,6 @@ do { \
subsequent accesses occur to other fields in the same word of the
structure, but to different bytes.
`SLOW_ZERO_EXTEND'
Define this macro if zero-extension (of a `char' or `short' to an
`int') can be done faster if the destination is a register that is
known to be zero.
If you define this macro, you must have instruction patterns that
recognize RTL structures like this:
(set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
and likewise for `HImode'.
`SLOW_UNALIGNED_ACCESS'
Define this macro to be the value 1 if unaligned accesses have a
cost many times greater than aligned accesses, for example if they

3
gcc/config/clipper/clipper.h
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@ -796,9 +796,6 @@ do \
#define MOVE_RATIO 20
/* Define this if zero-extension is slow (more than one real instruction). */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0

3
gcc/config/convex/convex.h
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@ -1031,9 +1031,6 @@ enum reg_class {
in one reasonably fast instruction. */
#define MOVE_MAX 8
/* Define this if zero-extension is slow (more than one real instruction). */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS (! TARGET_C2)

11
gcc/config/d30v/d30v.h
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@ -3432,17 +3432,6 @@ extern const char *d30v_branch_cost_string;
same word of the structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 1
/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
be done faster if the destination is a register that is known to be zero.
If you define this macro, you must have instruction patterns that recognize
RTL structures like this:
(set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
and likewise for `HImode'. */
#define SLOW_ZERO_EXTEND 0
/* Define this macro to be the value 1 if unaligned accesses have a cost many
times greater than aligned accesses, for example if they are emulated in a
trap handler.

4
gcc/config/dsp16xx/dsp16xx.h
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@ -1565,10 +1565,6 @@ extern struct dsp16xx_frame_info current_frame_info;
loads. */
#define SLOW_BYTE_ACCESS 1
/* Define this macro if zero-extension (of a char or short to an int) can
be done faster if the destination is a register that is know to be zero. */
/* #define SLOW_ZERO_EXTEND */
/* Define this macro if unaligned accesses have a cost many times greater than
aligned accesses, for example if they are emulated in a trap handler */
/* define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) */

3
gcc/config/elxsi/elxsi.h
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@ -577,9 +577,6 @@ enum reg_class { NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
in one reasonably fast instruction. */
#define MOVE_MAX 8
/* Define this if zero-extension is slow (more than one real instruction). */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0

11
gcc/config/fr30/fr30.h
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@ -1359,17 +1359,6 @@ do \
same word of the structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 1
/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
be done faster if the destination is a register that is known to be zero.
If you define this macro, you must have instruction patterns that recognize
RTL structures like this:
(set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
and likewise for `HImode'. */
#define SLOW_ZERO_EXTEND 0
/*}}}*/
/*{{{ Dividing the output into sections. */

3
gcc/config/h8300/h8300.h
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@ -965,9 +965,6 @@ struct cum_arg
#define MOVE_MAX (TARGET_H8300H || TARGET_H8300S ? 4 : 2)
#define MAX_MOVE_MAX 4
/* Define this if zero-extension is slow (more than one real instruction). */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS TARGET_SLOWBYTE

4
gcc/config/i370/i370.h
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@ -874,10 +874,6 @@ enum reg_class
#define MOVE_MAX 256
/* Define this if zero-extension is slow (more than one real instruction). */
#define SLOW_ZERO_EXTEND 1
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 1

13
gcc/config/i386/i386.h
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@ -2681,19 +2681,6 @@ do { \
/* Nonzero if access to memory by shorts is slow and undesirable. */
#define SLOW_SHORT_ACCESS 0
/* Define this macro if zero-extension (of a `char' or `short' to an
`int') can be done faster if the destination is a register that is
known to be zero.
If you define this macro, you must have instruction patterns that
recognize RTL structures like this:
(set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
and likewise for `HImode'. */
/* #define SLOW_ZERO_EXTEND */
/* Define this macro to be the value 1 if unaligned accesses have a
cost many times greater than aligned accesses, for example if they
are emulated in a trap handler.

3
gcc/config/m68k/m68k.h
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@ -1529,9 +1529,6 @@ __transfer_from_trampoline () \
in one reasonably fast instruction. */
#define MOVE_MAX 4
/* Define this if zero-extension is slow (more than one real instruction). */
#define SLOW_ZERO_EXTEND
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0

3
gcc/config/mips/mips.h
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@ -3378,9 +3378,6 @@ while (0)
#define STORE_FLAG_VALUE 1
/* Define this if zero-extension is slow (more than one real instruction). */
#define SLOW_ZERO_EXTEND
/* Define this to be nonzero if shift instructions ignore all but the low-order
few bits. */
#define SHIFT_COUNT_TRUNCATED 1

3
gcc/config/ns32k/ns32k.h
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@ -1116,9 +1116,6 @@ while (0)
We have a smart movstrsi insn */
#define MOVE_RATIO 0
/* Define this if zero-extension is slow (more than one real instruction). */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0

3
gcc/config/pdp11/pdp11.h
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@ -888,9 +888,6 @@ extern int may_call_alloca;
#define MOVE_MAX 2
/* Zero extension is faster if the target is known to be zero */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by byte is slow and undesirable. -
*/
#define SLOW_BYTE_ACCESS 0

5
gcc/config/pj/pj.h
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@ -932,11 +932,6 @@ struct pj_args
#define SHORT_IMMEDIATES_SIGN_EXTEND
/* Define this if zero-extension is slow (more than one real
instruction). */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is no faster than for words. */
#define SLOW_BYTE_ACCESS 1

4
gcc/config/s390/s390.h
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@ -1061,10 +1061,6 @@ CUMULATIVE_ARGS;
#define MOVE_MAX 256
/* Define this if zero-extension is slow (more than one real instruction). */
#define SLOW_ZERO_EXTEND
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 1

4
gcc/config/sh/sh.h
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@ -1682,10 +1682,6 @@ extern int current_function_anonymous_args;
/* Define if loading short immediate values into registers sign extends. */
#define SHORT_IMMEDIATES_SIGN_EXTEND
/* Define this if zero-extension is slow (more than one real instruction).
On the SH, it's only one instruction. */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is no faster than for words. */
#define SLOW_BYTE_ACCESS 1

11
gcc/config/stormy16/stormy16.h
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@ -3193,17 +3193,6 @@ do { \
same word of the structure, but to different bytes. */
#define SLOW_BYTE_ACCESS 0
/* Define this macro if zero-extension (of a `char' or `short' to an `int') can
be done faster if the destination is a register that is known to be zero.
If you define this macro, you must have instruction patterns that recognize
RTL structures like this:
(set (strict_low_part (subreg:QI (reg:SI ...) 0)) ...)
and likewise for `HImode'. */
#define SLOW_ZERO_EXTEND 0
/* Define this macro to be the value 1 if unaligned accesses have a cost many
times greater than aligned accesses, for example if they are emulated in a
trap handler.

3
gcc/config/v850/v850.h
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@ -1031,9 +1031,6 @@ do { \
than accessing full words. */
#define SLOW_BYTE_ACCESS 1
/* Define this if zero-extension is slow (more than one real instruction). */
#define SLOW_ZERO_EXTEND
/* According expr.c, a value of around 6 should minimize code size, and
for the V850 series, that's our primary concern. */
#define MOVE_RATIO 6

3
gcc/config/vax/vax.h
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@ -807,9 +807,6 @@ enum reg_class { NO_REGS, ALL_REGS, LIM_REG_CLASSES };
in one reasonably fast instruction. */
#define MOVE_MAX 8
/* Define this if zero-extension is slow (more than one real instruction). */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0

3
gcc/config/we32k/we32k.h
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@ -599,9 +599,6 @@ enum reg_class { NO_REGS, GENERAL_REGS,
in one reasonably fast instruction. */
#define MOVE_MAX 4
/* Define this if zero-extension is slow (more than one real instruction). */
/* #define SLOW_ZERO_EXTEND */
/* Nonzero if access to memory by bytes is slow and undesirable. */
#define SLOW_BYTE_ACCESS 0

16
gcc/doc/tm.texi
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@ -5176,22 +5176,6 @@ faster than word accesses, using word accesses is preferable since it
may eliminate subsequent memory access if subsequent accesses occur to
other fields in the same word of the structure, but to different bytes.
@findex SLOW_ZERO_EXTEND
@item SLOW_ZERO_EXTEND
Define this macro if zero-extension (of a @code{char} or @code{short}
to an @code{int}) can be done faster if the destination is a register
that is known to be zero.
If you define this macro, you must have instruction patterns that
recognize RTL structures like this:
@smallexample
(set (strict_low_part (subreg:QI (reg:SI @dots{}) 0)) @dots{})
@end smallexample
@noindent
and likewise for @code{HImode}.
@findex SLOW_UNALIGNED_ACCESS
@item SLOW_UNALIGNED_ACCESS (@var{mode}, @var{alignment})
Define this macro to be the value 1 if memory accesses described by the

11
gcc/expmed.c
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@ -1621,16 +1621,7 @@ extract_fixed_bit_field (tmode, op0, offset, bitsize, bitpos,
/* Unless the msb of the field used to be the msb when we shifted,
mask out the upper bits. */
if (GET_MODE_BITSIZE (mode) != bitpos + bitsize
#if 0
#ifdef SLOW_ZERO_EXTEND
/* Always generate an `and' if
we just zero-extended op0 and SLOW_ZERO_EXTEND, since it
will combine fruitfully with the zero-extend. */
|| tmode != mode
#endif
#endif
)
if (GET_MODE_BITSIZE (mode) != bitpos + bitsize)
return expand_binop (GET_MODE (op0), and_optab, op0,
mask_rtx (GET_MODE (op0), 0, bitsize, 0),
target, 1, OPTAB_LIB_WIDEN);

3
gcc/system.h
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@ -604,7 +604,8 @@ typedef char _Bool;
DOESNT_NEED_UNWINDER EH_TABLE_LOOKUP OBJC_SELECTORS_WITHOUT_LABELS \
OMIT_EH_TABLE EASY_DIV_EXPR IMPLICIT_FIX_EXPR \
LONGJMP_RESTORE_FROM_STACK MAX_INT_TYPE_SIZE ASM_IDENTIFY_GCC \
STDC_VALUE TRAMPOLINE_ALIGN ASM_IDENTIFY_GCC_AFTER_SOURCE
STDC_VALUE TRAMPOLINE_ALIGN ASM_IDENTIFY_GCC_AFTER_SOURCE \
SLOW_ZERO_EXTEND
#endif /* IN_GCC */