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invoke.texi (-mgen-cell-microcode): Document.

2008-10-13  Andrew Pinski  <andrew_pinski@playstation.sony.com>
            Kaushal Kantawala <Kaushal_Kantawala@playstation.sony.com>
            Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
            Grace Cao  <grace_cao@playstation.sony.com>

        * doc/invoke.texi (-mgen-cell-microcode): Document.
        (-mwarn-cell-microcode): Document.
        * cfglayout.c (locator_location): Export.
        * rtl.h (locator_location): Define prototype.
        * config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): New predicate.
        * rs6000/rs6000-protos.h (rs6000_final_prescan_insn): Define prototype.
        * config/rs6000/rs6000.opt (mgen-cell-microcode): New option.
        (mwarn-cell-microcode): New option.
        * rs6000/rs6000.c (rs6000_cell_dont_microcode): Delete unused variable.
        (rs6000_override_options): Set rs6000_gen_cell_microcode if tuning for
        cell and not already set.
        Turn off string instructions if not generating cell microcode.
        (rs6000_final_prescan_insn): New function that warns about microcoded
        instructions.
        * config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Define.
        * config/rs6000/rs6000.md
        Replace cc_reg_not_cr0_operand with cc_reg_not_micro_cr0_operand if
        the instruction would have been microcoded on the Cell.
        Set cell_micro to always on unnamed patterns for the string instructions.
        (cell_micro): Update definition, remove load/store conditional microcoded.
        (sign_extend:DI): Define new pattern for non microcoded version.
        (sign_extend:SI): Likewise.
        (compare (div:P)): Set cell_micro to not.
        (andsi3): Define as an expand.
        (andsi3_mc): New pattern.
        (andsi3_nomc): New pattern.
        (andsi3_internal0_nomc): New pattern.
        (andsi3_internal2): Rename to ...
        (andsi3_internal2_mc): this and enable iff generating microcode.
        (andsi3_internal3): Rename to ...
        (andsi3_internal3_mc): this and enable iff generating microcode.
        (andsi3_internal4): Enable iif generating microcode.
        (andsi3_internal5): Rename to ..
        (andsi3_internal5_mc): this and enable iff generating microcode.
        (andsi3_internal5_nomc): New pattern.
        (extzvdi_internal1): Enable iff generating microcode.
        (extzvdi_internal2): Likewise.
        (rotlsi3_internal7): Set cell_micro to always if non immediate form.
        (anddi3): Change to expand.
        (anddi3_mc): Rename from anddi3.
        (anddi3_no_mc): New pattern.
        (anddi3_internal2): Rename to ..
        (anddi3_internal2_mc): this and enable iff generating microcode.
        (anddi3_internal2_nomc): New pattern.
        (anddi3_internal3): Rename to ..
        (anddi3_internal3_mc): this and enable iff generating microcode.
        (anddi3_internal3_nomc): New pattern.
        (movti_string): Set cell_micro to always if TARGET_STRING.
        (stmsi8): Set cell_micro to always.
        (stmsi7): Likewise.
        (stmsi6): Likewise.
        (stmsi5): Likewise.
        (stmsi4): Likewise.
        (stmsi3): Likewise.
        (stmsi8_power): Likewise.
        (stmsi7_power): Likewise.
        (stmsi6_power): Likewise.
        (stmsi5_power): Likewise.
        (stmsi4_power): Likewise.
        (stmsi3_power): Likewise.
        (movsi_update2): Enable iff generating microcode.
        (movhi_update3): Likewise.
        (lmw): Set cell_micro to always.



Co-Authored-By: Grace Cao <grace_cao@playstation.sony.com>
Co-Authored-By: Kaushal Kantawala <Kaushal_Kantawala@playstation.sony.com>
Co-Authored-By: Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>

From-SVN: r141094
This commit is contained in:
Andrew Pinski 2008-10-13 19:57:31 +00:00 committed by Andrew Pinski
parent 0adef32bee
commit c921bad877
10 changed files with 404 additions and 139 deletions

@ -1,3 +1,72 @@
2008-10-13 Andrew Pinski <andrew_pinski@playstation.sony.com>
Kaushal Kantawala <Kaushal_Kantawala@playstation.sony.com>
Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
Grace Cao <grace_cao@playstation.sony.com>
* doc/invoke.texi (-mgen-cell-microcode): Document.
(-mwarn-cell-microcode): Document.
* cfglayout.c (locator_location): Export.
* rtl.h (locator_location): Define prototype.
* config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): New predicate.
* rs6000/rs6000-protos.h (rs6000_final_prescan_insn): Define prototype.
* config/rs6000/rs6000.opt (mgen-cell-microcode): New option.
(mwarn-cell-microcode): New option.
* rs6000/rs6000.c (rs6000_cell_dont_microcode): Delete unused variable.
(rs6000_override_options): Set rs6000_gen_cell_microcode if tuning for
cell and not already set.
Turn off string instructions if not generating cell microcode.
(rs6000_final_prescan_insn): New function that warns about microcoded
instructions.
* config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Define.
* config/rs6000/rs6000.md
Replace cc_reg_not_cr0_operand with cc_reg_not_micro_cr0_operand if
the instruction would have been microcoded on the Cell.
Set cell_micro to always on unnamed patterns for the string instructions.
(cell_micro): Update definition, remove load/store conditional microcoded.
(sign_extend:DI): Define new pattern for non microcoded version.
(sign_extend:SI): Likewise.
(compare (div:P)): Set cell_micro to not.
(andsi3): Define as an expand.
(andsi3_mc): New pattern.
(andsi3_nomc): New pattern.
(andsi3_internal0_nomc): New pattern.
(andsi3_internal2): Rename to ...
(andsi3_internal2_mc): this and enable iff generating microcode.
(andsi3_internal3): Rename to ...
(andsi3_internal3_mc): this and enable iff generating microcode.
(andsi3_internal4): Enable iif generating microcode.
(andsi3_internal5): Rename to ..
(andsi3_internal5_mc): this and enable iff generating microcode.
(andsi3_internal5_nomc): New pattern.
(extzvdi_internal1): Enable iff generating microcode.
(extzvdi_internal2): Likewise.
(rotlsi3_internal7): Set cell_micro to always if non immediate form.
(anddi3): Change to expand.
(anddi3_mc): Rename from anddi3.
(anddi3_no_mc): New pattern.
(anddi3_internal2): Rename to ..
(anddi3_internal2_mc): this and enable iff generating microcode.
(anddi3_internal2_nomc): New pattern.
(anddi3_internal3): Rename to ..
(anddi3_internal3_mc): this and enable iff generating microcode.
(anddi3_internal3_nomc): New pattern.
(movti_string): Set cell_micro to always if TARGET_STRING.
(stmsi8): Set cell_micro to always.
(stmsi7): Likewise.
(stmsi6): Likewise.
(stmsi5): Likewise.
(stmsi4): Likewise.
(stmsi3): Likewise.
(stmsi8_power): Likewise.
(stmsi7_power): Likewise.
(stmsi6_power): Likewise.
(stmsi5_power): Likewise.
(stmsi4_power): Likewise.
(stmsi3_power): Likewise.
(movsi_update2): Enable iff generating microcode.
(movhi_update3): Likewise.
(lmw): Set cell_micro to always.
2008-10-13 Richard Sandiford <rdsandiford@googlemail.com>
* config/s390/s390.md (UNSPEC_POOL_OFFSET): New constant.

@ -495,7 +495,7 @@ insn_scope (const_rtx insn)
}
/* Return line number of the statement specified by the locator. */
static location_t
location_t
locator_location (int loc)
{
int max = VEC_length (int, locations_locators_locs);

@ -104,6 +104,14 @@
|| REGNO (op) > LAST_VIRTUAL_REGISTER
|| CR_REGNO_NOT_CR0_P (REGNO (op))")))
;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
(define_predicate "cc_reg_not_micro_cr0_operand"
(and (match_operand 0 "register_operand")
(match_test "GET_CODE (op) != REG
|| REGNO (op) > LAST_VIRTUAL_REGISTER
|| (rs6000_gen_cell_microcode && CR_REGNO_NOT_CR0_P (REGNO (op)))
|| (!rs6000_gen_cell_microcode && CR_REGNO_P (REGNO (op)))")))
;; Return 1 if op is a constant integer valid for D field
;; or non-special register register.
(define_predicate "reg_or_short_operand"

@ -181,5 +181,7 @@ extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
char *output_call (rtx, rtx *, int, int);
#endif
void rs6000_final_prescan_insn (rtx, rtx *operand, int num_operands);
extern bool rs6000_hard_regno_mode_ok_p[][FIRST_PSEUDO_REGISTER];
#endif /* rs6000-protos.h */

@ -143,8 +143,6 @@ struct rs6000_cpu_select rs6000_select[3] =
{ (const char *)0, "-mtune=", 1, 0 },
};
static GTY(()) bool rs6000_cell_dont_microcode;
/* Always emit branch hint bits. */
static GTY(()) bool rs6000_always_hint;
@ -1609,9 +1607,16 @@ rs6000_override_options (const char *default_cpu)
error ("Spe not supported in this target");
}
/* Disable cell micro code if we are optimizing for the cell
and not optimizing for size. */
if (rs6000_gen_cell_microcode == -1)
rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
&& !optimize_size);
/* If we are optimizing big endian systems for space, use the load/store
multiple and string instructions. */
if (BYTES_BIG_ENDIAN && optimize_size)
multiple and string instructions unless we are not generating
Cell microcode. */
if (BYTES_BIG_ENDIAN && optimize_size && !rs6000_gen_cell_microcode)
target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
/* Don't allow -mmultiple or -mstring on little endian systems
@ -22794,4 +22799,31 @@ rs6000_stack_protect_fail (void)
: default_external_stack_protect_fail ();
}
void
rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
int num_operands ATTRIBUTE_UNUSED)
{
if (rs6000_warn_cell_microcode)
{
const char *temp;
int insn_code_number = recog_memoized (insn);
location_t location = locator_location (INSN_LOCATOR (insn));
/* Punt on insns we cannot recognize. */
if (insn_code_number < 0)
return;
temp = get_insn_template (insn_code_number, insn);
if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
warning_at (location, OPT_mwarn_cell_microcode,
"emitting microcode insn %s\t[%s] #%d",
temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
warning_at (location, OPT_mwarn_cell_microcode,
"emitting conditional microcode insn %s\t[%s] #%d",
temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
}
}
#include "gt-rs6000.h"

@ -1905,7 +1905,8 @@ do { \
/* Define this if some processing needs to be done immediately before
emitting code for an insn. */
/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */

File diff suppressed because it is too large Load Diff

@ -233,6 +233,14 @@ mlongcall
Target Report Var(rs6000_default_long_calls)
Avoid all range limits on call instructions
mgen-cell-microcode
Target Report Var(rs6000_gen_cell_microcode) Init(-1)
Generate Cell microcode
mwarn-cell-microcode
Target Var(rs6000_warn_cell_microcode) Init(0) Warning
Emitting warning when a Cell microcode is emitted
mwarn-altivec-long
Target Var(rs6000_warn_altivec_long) Init(1)
Warn about deprecated 'vector long ...' AltiVec type usage

@ -735,6 +735,7 @@ See RS/6000 and PowerPC Options.
-mspe -mno-spe @gol
-mspe=yes -mspe=no @gol
-mpaired @gol
-mgen-cell-microcode -mwarn-cell-microcode @gol
-mvrsave -mno-vrsave @gol
-mmulhw -mno-mulhw @gol
-mdlmzb -mno-dlmzb @gol
@ -13490,6 +13491,15 @@ enhancements.
@opindex mno-vrsave
Generate VRSAVE instructions when generating AltiVec code.
@item -mgen-cell-microcode
@opindex mgen-cell-microcode
Generate Cell microcode instructions
@item -mwarn-cell-microcode
@opindex mwarn-cell-microcode
Warning when a Cell microcode instruction is going to emitted. An example
of a Cell microcode instruction is a variable shift.
@item -msecure-plt
@opindex msecure-plt
Generate code that allows ld and ld.so to build executables and shared

@ -1637,6 +1637,7 @@ extern rtx prev_cc0_setter (rtx);
/* In cfglayout.c */
extern int insn_line (const_rtx);
extern const char * insn_file (const_rtx);
extern location_t locator_location (int);
extern int locator_line (int);
extern const char * locator_file (int);
extern bool locator_eq (int, int);