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Add ia64 port.

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From-SVN: r32438
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Jim Wilson 2000-03-09 00:26:04 +00:00 committed by Jim Wilson
parent 5194cf0890
commit c65ebc55ca
17 changed files with 11248 additions and 0 deletions
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6
gcc/ChangeLog
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Wed Mar 8 16:19:42 2000 Jim Wilson <wilson@cygnus.com>
* configure.in (ia64*-*-elf*, ia64*-*-linux*): New.
* configure: Regenerate.
* config/ia64: New.
2000-03-08 Zack Weinberg <zack@wolery.cumb.org>
* Makefile.in (LIBCPP_DEPS): New macro.

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The gcse.c patch fixes an optimization problem. This is probably not the right
solution, but it was quick. I will replace with a better solution later.
The libio/libstdc++ patches are useful if you have a version of glibc without
thread support. There is no official ia64 glibc version yet, and some of the
unofficial ones in common use are missing thread support. libio/libstdc++
assume that glibc always has thread support, so we need to patch them until
the official ia64 glibc is available.
Index: gcc/gcse.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/gcse.c,v
retrieving revision 1.87
diff -p -r1.87 gcse.c
*** gcse.c 2000/01/11 14:59:28 1.87
--- gcse.c 2000/02/16 04:17:06
*************** try_replace_reg (from, to, insn)
*** 4039,4045 ****
information. */
if (!success && !note)
{
! if (!set)
return 0;
note = REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL,
copy_rtx (SET_SRC (set)),
--- 4039,4048 ----
information. */
if (!success && !note)
{
! /* Don't add a REG_EQUAL note for a CCmode destination, because this
! confuses the code in cse.c that simplifies compare and branch
! instructions. */
! if (!set || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) == MODE_CC)
return 0;
note = REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL,
copy_rtx (SET_SRC (set)),
Index: libio/configure.in
===================================================================
RCS file: /cvs/cvsfiles/devo/libio/configure.in,v
retrieving revision 1.57
diff -p -r1.57 configure.in
*** configure.in 1999/10/26 03:42:26 1.57
--- configure.in 2000/02/16 04:17:56
*************** case "${target}" in
*** 57,62 ****
--- 57,64 ----
frags="linux.mt linuxaxp1.mt mtsafe.mt" ;;
*-linux-gnulibc1)
frags=linuxlibc1.mt ;;
+ # ??? glibc does not have thread support yet, so we can't use mtsafe.mt.
+ ia64*-linux-gnu) frags="linux.mt" ;;
*-linux-gnu) frags="linux.mt mtsafe.mt" ;;
*-sco3.2v[45]*) frags=sco4.mt ;;
*-isc*) frags=isc.mt ;;
Index: libstdc++/configure.in
===================================================================
RCS file: /cvs/cvsfiles/devo/libstdc++/configure.in,v
retrieving revision 1.46
diff -p -r1.46 configure.in
*** configure.in 1999/09/21 19:26:16 1.46
--- configure.in 2000/02/16 04:17:57
*************** fi
*** 89,94 ****
--- 89,96 ----
case "${target}" in
alpha*-*-linux-gnulibc1) frags="${frags} linux.mt" ;;
powerpc*-*-linux-gnulibc1) frags="${frags} linux.mt" ;;
+ # ??? ia64 glibc port does not have thread support yet.
+ ia64*-*-linux-gnu) ;;
*-*-linux-gnu) frags="${frags} linux.mt" ;;
*-*-openbsd*)
case "x${enable_threads}" in
Index: libstdc++/stl/stl_config.h
===================================================================
RCS file: /cvs/cvsfiles/devo/libstdc++/stl/stl_config.h,v
retrieving revision 1.17
diff -p -r1.17 stl_config.h
*** stl_config.h 1999/12/24 16:21:31 1.17
--- stl_config.h 2000/02/16 04:17:58
***************
*** 168,174 ****
# if defined(__linux__)
/* glibc pre 2.0 is very buggy. We have to disable thread for it.
It should be upgraded to glibc 2.0 or later. */
! # if !defined(_NOTHREADS) && __GLIBC__ >= 2 && defined(_G_USING_THUNKS)
# define __STL_PTHREADS
# ifdef __STRICT_ANSI__
/* Work around a bug in the glibc 2.0.x pthread.h. */
--- 168,175 ----
# if defined(__linux__)
/* glibc pre 2.0 is very buggy. We have to disable thread for it.
It should be upgraded to glibc 2.0 or later. */
! /* ??? ia64 glibc port does not have thread support yet. */
! # if !defined(_NOTHREADS) && __GLIBC__ >= 2 && defined(_G_USING_THUNKS) && !defined(__ia64__)
# define __STL_PTHREADS
# ifdef __STRICT_ANSI__
/* Work around a bug in the glibc 2.0.x pthread.h. */

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/* Copyright (C) 2000 Free Software Foundation, Inc.
Contributed by Jes Sorensen, <Jes.Sorensen@cern.ch>
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with the GNU C Library; see the file COPYING.LIB. If not,
write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
.section .ctors,"aw","progbits"
.align 8
__CTOR_LIST__:
data8 -1
.section .dtors,"aw","progbits"
.align 8
__DTOR_LIST__:
data8 -1
.section .sdata
.type dtor_ptr#,@object
.size dtor_ptr#,8
dtor_ptr:
data8 __DTOR_LIST__# + 8
.global __dso_handle#
.type __dso_handle#,@object
.size __dso_handle#,8
#ifdef SHARED
.section .data
__dso_handle:
data8 __dso_handle#
#else
.section .bss
__dso_handle:
data8 0
#endif
/*
* Fragment of the ELF _fini routine that invokes our dtor cleanup.
*
* The code going into .fini is spread all over the place, thus we need
* to save gp in order to make sure that other bits don't get into any
* nasty surprises by expecting a gp that has suddenly changed.
*/
.section .fini,"ax","progbits"
{ .mfb
st8 [r12] = gp, -16
br.call.sptk.many b0 = __do_global_dtors_aux#
;;
}
{ .mmi
adds r12 = 16, r12
;;
ld8 gp = [r12]
;;
}
.text
.align 16
.proc __do_global_dtors_aux#
__do_global_dtors_aux:
#ifndef SHARED
{ .mii
alloc loc2 = ar.pfs, 0, 3, 0, 0
addl loc0 = @gprel(dtor_ptr#), gp
mov loc1 = b0
}
#else
/*
if (__cxa_finalize)
__cxa_finalize(__dso_handle)
*/
{ .mii
alloc loc2 = ar.pfs, 1, 3, 0, 0
addl loc0 = @gprel(dtor_ptr#), gp
addl r16 = @ltoff(@fptr(__cxa_finalize#)), gp
;;
}
{ .mmi
ld8 r16 = [r16]
;;
addl r32 = @ltoff(__dso_handle#), gp
cmp.ne p7, p0 = r0, r16
;;
}
{ .mmi
ld8 r32 = [r32]
(p7) ld8 r18 = [r16], 8
mov loc1 = b0
;;
}
{ .mib
(p7) ld8 gp = [r16]
(p7) mov b6 = r18
(p7) br.call.sptk.many b0 = b6
}
#endif
/*
do {
dtor_ptr++;
(*(dtor_ptr-1)) ();
} while (dtor_ptr);
*/
{ .bbb
br.sptk.few 1f
;;
}
0:
{ .mmi
st8 [loc0] = r15
ld8 r17 = [r16], 8
;;
}
{ .mib
ld8 gp = [r16]
mov b6 = r17
br.call.sptk.many b0 = b6
}
1:
{ .mmi
ld8 r15 = [loc0]
;;
ld8 r16 = [r15], 8
;;
}
{ .mfb
cmp.ne p6, p0 = r0, r16
(p6) br.cond.sptk.few 0b
}
{ .mii
mov b0 = loc1
mov ar.pfs = loc2
}
{ .bbb
br.ret.sptk.many b0
;;
}
.endp __do_global_dtors_aux#
#ifdef SHARED
.weak __cxa_finalize#
#endif

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/* Copyright (C) 2000 Free Software Foundation, Inc.
Contributed by Jes Sorensen, <Jes.Sorensen@cern.ch>
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Library General Public License for more details.
You should have received a copy of the GNU Library General Public
License along with the GNU C Library; see the file COPYING.LIB. If not,
write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
.section .ctors,"aw","progbits"
.align 8
__CTOR_END__:
data8 0
.section .dtors,"aw","progbits"
.align 8
__DTOR_END__:
data8 0
/*
* Fragment of the ELF _init routine that invokes our dtor cleanup.
*
* The code going into .init is spread all over the place, thus we need
* to save gp in order to make sure that other bits don't get into any
* nasty surprises by expecting a gp that has suddenly changed.
*/
.section .init,"ax","progbits"
{ .mfb
st8 [r12] = gp, -16
br.call.sptk.many b0 = __do_global_ctors_aux
;;
}
{ .mmi
adds r12 = 16, r12
;;
ld8 gp = [r12]
;;
}
.text
.align 16
.proc __do_global_ctors_aux#
__do_global_ctors_aux:
/*
for (loc0 = __CTOR_END__-1; *p != -1; --p)
(*p) ();
*/
{ .mii
alloc loc2 = ar.pfs, 0, 4, 0, 0
addl loc0 = @ltoff(__CTOR_END__# - 8), gp
cmp.ne p6, p0 = r0, r0
;;
}
{ .mfi
ld8 loc0 = [loc0]
mov loc1 = b0
}
0:
{ .mmi
(p6) ld8 r15 = [loc3], 8
;;
(p6) ld8 gp = [loc3]
(p6) mov b6 = r15
}
{ .mfb
ld8 loc3 = [loc0], -8
(p6) br.call.sptk.many b0 = b6
;;
}
{ .mfb
cmp.ne p6, p0 = -1, loc3
(p6) br.cond.sptk.few 0b
}
{ .mii
mov ar.pfs = loc2
mov b0 = loc1
}
{ .bbb
br.ret.sptk.many b0
;;
}
.endp __do_global_ctors_aux#

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/* Definitions for embedded ia64-elf target. */
#include "ia64/ia64.h"
#include "elfos.h"
#include "sysv4.h"
/* svr4.h links with crti.o/crtn.o, but elfos.h does not. We override elfos.h
so that we can use the standard ELF Unix method. */
#undef ENDFILE_SPEC
#define ENDFILE_SPEC "crtend.o%s crtn.o%s"
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared: \
%{!symbolic: \
%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}}\
crti.o%s crtbegin.o%s"
/* End of elf.h */

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/* Definitions of target machine for GNU compiler for IA-64.
Copyright (C) 1999 Cygnus Solutions.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* Variables defined in ia64.c. */
#ifdef RTX_CODE
extern rtx ia64_compare_op0, ia64_compare_op1;
#endif
/* Functions defined in ia64.c */
#ifdef RTX_CODE
extern int call_operand PARAMS((rtx, enum machine_mode));
extern int sdata_symbolic_operand PARAMS((rtx, enum machine_mode));
extern int symbolic_operand PARAMS((rtx, enum machine_mode));
extern int function_operand PARAMS((rtx, enum machine_mode));
extern int setjmp_operand PARAMS((rtx, enum machine_mode));
extern int move_operand PARAMS((rtx, enum machine_mode));
extern int reg_or_0_operand PARAMS((rtx, enum machine_mode));
extern int reg_or_6bit_operand PARAMS((rtx, enum machine_mode));
extern int reg_or_8bit_operand PARAMS((rtx, enum machine_mode));
extern int reg_or_8bit_adjusted_operand PARAMS((rtx, enum machine_mode));
extern int reg_or_8bit_and_adjusted_operand PARAMS((rtx, enum machine_mode));
extern int reg_or_14bit_operand PARAMS((rtx, enum machine_mode));
extern int reg_or_22bit_operand PARAMS((rtx, enum machine_mode));
extern int shift_count_operand PARAMS((rtx, enum machine_mode));
extern int shift_32bit_count_operand PARAMS((rtx, enum machine_mode));
extern int shladd_operand PARAMS((rtx, enum machine_mode));
extern int reg_or_fp01_operand PARAMS((rtx, enum machine_mode));
extern int normal_comparison_operator PARAMS((rtx, enum machine_mode));
extern int adjusted_comparison_operator PARAMS((rtx, enum machine_mode));
extern int call_multiple_values_operation PARAMS((rtx, enum machine_mode));
#endif
extern int ia64_rap_fp_offset PARAMS((void));
extern unsigned int ia64_compute_frame_size PARAMS((int));
extern void save_restore_insns PARAMS((int));
extern void ia64_expand_prologue PARAMS((void));
extern void ia64_expand_epilogue PARAMS((void));
extern void ia64_function_prologue PARAMS((FILE *, int));
extern void ia64_funtion_epilogue PARAMS((FILE *, int));
extern int ia64_direct_return PARAMS((void));
#ifdef TREE_CODE
extern void ia64_setup_incoming_varargs PARAMS((CUMULATIVE_ARGS, int, tree,
int *, int));
#ifdef RTX_CODE
extern rtx ia64_function_arg PARAMS((CUMULATIVE_ARGS *, enum machine_mode,
tree, int, int));
extern void ia64_init_builtins PARAMS((void));
extern rtx ia64_expand_builtin PARAMS((tree, rtx, rtx, enum machine_mode, int));
#endif
extern int ia64_function_arg_partial_nregs PARAMS((CUMULATIVE_ARGS *,
enum machine_mode,
tree, int));
extern void ia64_function_arg_advance PARAMS((CUMULATIVE_ARGS *,
enum machine_mode,
tree, int));
#ifdef RTX_CODE
extern void ia64_va_start PARAMS((int, tree, rtx));
extern rtx ia64_va_arg PARAMS((tree, tree));
#endif
extern int ia64_return_in_memory PARAMS((tree));
#ifdef RTX_CODE
extern rtx ia64_function_value PARAMS((tree, tree));
#endif
#endif
#ifdef RTX_CODE
extern void ia64_print_operand_address PARAMS((FILE *, rtx));
extern void ia64_print_operand PARAMS((FILE *, rtx, int));
extern enum reg_class ia64_secondary_reload_class PARAMS((enum reg_class,
enum machine_mode,
rtx));
#endif
#ifdef TREE_CODE
extern void ia64_asm_output_external PARAMS((FILE *, tree, char *));
#endif
extern void ia64_override_options PARAMS((void));
#ifdef RTX_CODE
extern void ia64_reorg PARAMS((rtx));
#endif
extern int ia64_epilogue_uses PARAMS((int));
#ifdef TREE_CODE
extern int ia64_valid_type_attribute PARAMS((tree, tree, tree, tree));
extern void ia64_encode_section_info PARAMS((tree));
#endif

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#ifndef _IA64INTRIN_H_INCLUDED
#define _IA64INTRIN_H_INCLUDED
void __sync_synchronize (void);
int __sync_val_compare_and_swap_si (int *, int, int);
long __sync_val_compare_and_swap_di (long *, long, long);
#define __sync_val_compare_and_swap(A,B,C) ((sizeof (*(A)) == sizeof(int)) ? __sync_val_compare_and_swap_si((int *)(A),(int)(B),(int)(C)) : __sync_val_compare_and_swap_di((long *)(A),(long)(B),(long)(C)))
int __sync_bool_compare_and_swap_si (int *, int, int);
long __sync_bool_compare_and_swap_di (long *, long, long);
#define __sync_bool_compare_and_swap(A,B,C) ((sizeof (*(A)) == sizeof(int)) ? __sync_bool_compare_and_swap_si((int *)(A),(int)(B),(int)(C)) : __sync_bool_compare_and_swap_di((long *)(A),(long)(B),(long)(C)))
void __sync_lock_release_si (int *);
void __sync_lock_release_di (long *);
#define __sync_lock_release(A) ((sizeof (*(A)) == sizeof(int)) ? __sync_lock_release_si((int *)(A)) : __sync_lock_release_di((long *)(A)))
int __sync_lock_test_and_set_si (int *, int);
long __sync_lock_test_and_set_di (long *, long);
#define __sync_lock_test_and_set(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_lock_test_and_set_si((int *)(A),(int)(B)) : __sync_lock_test_and_set_di((long *)(A),(long)(B)))
int __sync_fetch_and_add_si (int *, int);
int __sync_fetch_and_sub_si (int *, int);
int __sync_fetch_and_and_si (int *, int);
int __sync_fetch_and_or_si (int *, int);
int __sync_fetch_and_xor_si (int *, int);
int __sync_fetch_and_nand_si (int *, int);
long __sync_fetch_and_add_di (long *, long);
long __sync_fetch_and_sub_di (long *, long);
long __sync_fetch_and_and_di (long *, long);
long __sync_fetch_and_or_di (long *, long);
long __sync_fetch_and_xor_di (long *, long);
long __sync_fetch_and_nand_di (long *, long);
#define __sync_fetch_and_add(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_fetch_and_add_si((int *)(A),(int)(B)) : __sync_fetch_and_add_di((long *)(A),(long)(B)))
#define __sync_fetch_and_sub(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_fetch_and_sub_si((int *)(A),(int)(B)) : __sync_fetch_and_sub_di((long *)(A),(long)(B)))
#define __sync_fetch_and_and(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_fetch_and_and_si((int *)(A),(int)(B)) : __sync_fetch_and_and_di((long *)(A),(long)(B)))
#define __sync_fetch_and_or(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_fetch_and_or_si((int *)(A),(int)(B)) : __sync_fetch_and_or_di((long *)(A),(long)(B)))
#define __sync_fetch_and_xor(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_fetch_and_xor_si((int *)(A),(int)(B)) : __sync_fetch_and_xor_di((long *)(A),(long)(B)))
#define __sync_fetch_and_nand(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_fetch_and_nand_si((int *)(A),(int)(B)) : __sync_fetch_and_nand_di((long *)(A),(long)(B)))
int __sync_add_and_fetch_si (int *, int);
int __sync_sub_and_fetch_si (int *, int);
int __sync_and_and_fetch_si (int *, int);
int __sync_or_and_fetch_si (int *, int);
int __sync_xor_and_fetch_si (int *, int);
int __sync_nand_and_fetch_si (int *, int);
long __sync_add_and_fetch_di (long *, long);
long __sync_sub_and_fetch_di (long *, long);
long __sync_and_and_fetch_di (long *, long);
long __sync_or_and_fetch_di (long *, long);
long __sync_xor_and_fetch_di (long *, long);
long __sync_nand_and_fetch_di (long *, long);
#define __sync_add_and_fetch(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_add_and_fetch_si((int *)(A),(int)(B)) : __sync_add_and_fetch_di((long *)(A),(long)(B)))
#define __sync_sub_and_fetch(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_sub_and_fetch_si((int *)(A),(int)(B)) : __sync_sub_and_fetch_di((long *)(A),(long)(B)))
#define __sync_and_and_fetch(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_and_and_fetch_si((int *)(A),(int)(B)) : __sync_and_and_fetch_di((long *)(A),(long)(B)))
#define __sync_or_and_fetch(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_or_and_fetch_si((int *)(A),(int)(B)) : __sync_or_and_fetch_di((long *)(A),(long)(B)))
#define __sync_xor_and_fetch(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_xor_and_fetch_si((int *)(A),(int)(B)) : __sync_xor_and_fetch_di((long *)(A),(long)(B)))
#define __sync_nand_and_fetch(A,B) ((sizeof (*(A)) == sizeof(int)) ? __sync_nand_and_fetch_si((int *)(A),(int)(B)) : __sync_nand_and_fetch_di((long *)(A),(long)(B)))
#endif

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#ifdef L__divdf3
// Compute a 64-bit IEEE double quotient.
//
// From the Intel IA-64 Optimization Guide, choose the minimum latency
// alternative.
//
// farg0 holds the dividend. farg1 holds the divisor.
.text
.align 16
.global __divdf3
.proc __divdf3
__divdf3:
frcpa f10, p6 = farg0, farg1
;;
(p6) fma.s1 f11 = farg0, f10, f0
(p6) fnma.s1 f12 = farg1, f10, f1
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fma.s1 f13 = f12, f12, f0
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fma.s1 f11 = f13, f11, f11
(p6) fma.s1 f12 = f13, f13, f0
(p6) fma.s1 f10 = f13, f10, f10
;;
(p6) fma.d.s1 f11 = f12, f11, f11
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fnma.d.s1 f8 = farg1, f11, farg0
;;
(p6) fma.d f10 = f8, f10, f11
;;
mov fret0 = f10
br.ret.sptk rp
;;
.endp __divdf3
#endif
#ifdef L__divsf3
// Compute a 32-bit IEEE float quotient.
//
// From the Intel IA-64 Optimization Guide, choose the minimum latency
// alternative.
//
// farg0 holds the dividend. farg1 holds the divisor.
.text
.align 16
.global __divsf3
.proc __divsf3
__divsf3:
frcpa f10, p6 = farg0, farg1
;;
(p6) fma.s1 f8 = farg0, f10, f0
(p6) fnma.s1 f9 = farg1, f10, f1
;;
(p6) fma.s1 f8 = f9, f8, f8
(p6) fma.s1 f9 = f9, f9, f0
;;
(p6) fma.s1 f8 = f9, f8, f8
(p6) fma.s1 f9 = f9, f9, f0
;;
(p6) fma.d.s1 f8 = f9, f8, f8
;;
(p6) fma.s f10 = f8, f1, f0
;;
mov fret0 = f10
br.ret.sptk rp
;;
.endp __divsf3
#endif
#ifdef L__divdi3
// Compute a 64-bit integer quotient.
//
// Use reciprocal approximation and Newton-Raphson iteration to compute the
// quotient. frcpa gives 8.6 significant bits, so we need 3 iterations
// to get more than the 64 bits of precision that we need for DImode.
//
// Must use max precision for the reciprocal computations to get 64 bits of
// precision.
//
// r32/f8 holds the dividend. r33/f9 holds the divisor.
// f10 holds the value 2.0. f11 holds the reciprocal approximation.
// f12 is a temporary.
.text
.align 16
.global __divdi3
.proc __divdi3
__divdi3:
.regstk 2,0,0,0
// Transfer inputs to FP registers.
setf.sig f8 = in0
setf.sig f9 = in1
;;
// Convert the inputs to FP, so that they won't be treated as unsigned.
fcvt.xf f8 = f8
fcvt.xf f9 = f9
;;
// Compute the reciprocal approximation.
frcpa f10, p6 = f8, f9
;;
// 3 Newton-Raphson iterations.
(p6) fma.s1 f11 = farg0, f10, f0
(p6) fnma.s1 f12 = farg1, f10, f1
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fma.s1 f13 = f12, f12, f0
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fma.s1 f11 = f13, f11, f11
(p6) fma.s1 f12 = f13, f13, f0
(p6) fma.s1 f10 = f13, f10, f10
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fnma.s1 f8 = f9, f11, f8
;;
(p6) fma f10 = f8, f10, f11
;;
// Round quotient to an integer.
fcvt.fx.trunc f8 = f10
;;
// Transfer result to GP registers.
getf.sig ret0 = f8
br.ret.sptk rp
;;
.endp __divdi3
#endif
#ifdef L__moddi3
// Compute a 64-bit integer modulus.
//
// Use reciprocal approximation and Newton-Raphson iteration to compute the
// quotient. frcpa gives 8.6 significant bits, so we need 3 iterations
// to get more than the 64 bits of precision that we need for DImode.
//
// Must use max precision for the reciprocal computations to get 64 bits of
// precision.
//
// r32/f8 holds the dividend. r33/f9 holds the divisor.
// f10 holds the value 2.0. f11 holds the reciprocal approximation.
// f12 is a temporary.
.text
.align 16
.global __moddi3
.proc __moddi3
__moddi3:
.regstk 2,0,0,0
// Transfer inputs to FP registers.
setf.sig f8 = in0
setf.sig f9 = in1
;;
// Convert the inputs to FP, so that they won't be treated as unsigned.
fcvt.xf f8 = f8
fcvt.xf f9 = f9
;;
// Compute the reciprocal approximation.
frcpa f10, p6 = f8, f9
;;
// 3 Newton-Raphson iterations.
(p6) fma.s1 f11 = farg0, f10, f0
(p6) fnma.s1 f12 = farg1, f10, f1
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fma.s1 f13 = f12, f12, f0
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fma.s1 f11 = f13, f11, f11
(p6) fma.s1 f12 = f13, f13, f0
(p6) fma.s1 f10 = f13, f10, f10
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fnma.s1 f12 = f9, f11, f8
;;
(p6) fma f10 = f12, f10, f11
;;
// Round quotient to an integer.
fcvt.fx.trunc f10 = f10
;;
// Renormalize.
fcvt.xf f10 = f10
;;
// Compute remainder.
fnma f8 = f10, f9, f8
;;
// Round remainder to an integer.
fcvt.fx.trunc f8 = f8
;;
// Transfer result to GP registers.
getf.sig ret0 = f8
br.ret.sptk rp
;;
.endp __moddi3
#endif
#ifdef L__udivdi3
// Compute a 64-bit unsigned integer quotient.
//
// Use reciprocal approximation and Newton-Raphson iteration to compute the
// quotient. frcpa gives 8.6 significant bits, so we need 3 iterations
// to get more than the 64 bits of precision that we need for DImode.
//
// Must use max precision for the reciprocal computations to get 64 bits of
// precision.
//
// r32/f8 holds the dividend. r33/f9 holds the divisor.
// f10 holds the value 2.0. f11 holds the reciprocal approximation.
// f12 is a temporary.
.text
.align 16
.global __udivdi3
.proc __udivdi3
__udivdi3:
.regstk 2,0,0,0
// Transfer inputs to FP registers.
setf.sig f8 = in0
setf.sig f9 = in1
;;
// Convert the inputs to FP, to avoid FP software-assist faults.
fcvt.xuf f8 = f8
fcvt.xuf f9 = f9
;;
// Compute the reciprocal approximation.
frcpa f10, p6 = f8, f9
;;
// 3 Newton-Raphson iterations.
(p6) fma.s1 f11 = farg0, f10, f0
(p6) fnma.s1 f12 = farg1, f10, f1
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fma.s1 f13 = f12, f12, f0
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fma.s1 f11 = f13, f11, f11
(p6) fma.s1 f12 = f13, f13, f0
(p6) fma.s1 f10 = f13, f10, f10
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fnma.s1 f8 = f9, f11, f8
;;
(p6) fma f10 = f8, f10, f11
;;
// Round quotient to an unsigned integer.
fcvt.fxu.trunc f8 = f10
;;
// Transfer result to GP registers.
getf.sig ret0 = f8
br.ret.sptk rp
;;
.endp __udivdi3
#endif
#ifdef L__umoddi3
// Compute a 64-bit unsigned integer modulus.
//
// Use reciprocal approximation and Newton-Raphson iteration to compute the
// quotient. frcpa gives 8.6 significant bits, so we need 3 iterations
// to get more than the 64 bits of precision that we need for DImode.
//
// Must use max precision for the reciprocal computations to get 64 bits of
// precision.
//
// r32/f8 holds the dividend. r33/f9 holds the divisor.
// f10 holds the value 2.0. f11 holds the reciprocal approximation.
// f12 is a temporary.
.text
.align 16
.global __umoddi3
.proc __umoddi3
__umoddi3:
.regstk 2,0,0,0
// Transfer inputs to FP registers.
setf.sig f8 = in0
setf.sig f9 = in1
;;
// Convert the inputs to FP, to avoid FP software assist faults.
fcvt.xuf f8 = f8
fcvt.xuf f9 = f9
;;
// Compute the reciprocal approximation.
frcpa f10, p6 = f8, f9
;;
// 3 Newton-Raphson iterations.
(p6) fma.s1 f11 = farg0, f10, f0
(p6) fnma.s1 f12 = farg1, f10, f1
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fma.s1 f13 = f12, f12, f0
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fma.s1 f11 = f13, f11, f11
(p6) fma.s1 f12 = f13, f13, f0
(p6) fma.s1 f10 = f13, f10, f10
;;
(p6) fma.s1 f11 = f12, f11, f11
(p6) fma.s1 f10 = f12, f10, f10
;;
(p6) fnma.s1 f12 = f9, f11, f8
;;
(p6) fma f10 = f12, f10, f11
;;
// Round quotient to an unsigned integer.
fcvt.fxu.trunc f10 = f10
;;
// Renormalize.
fcvt.xuf f10 = f10
;;
// Compute remainder.
fnma f8 = f10, f9, f8
;;
// Round remainder to an integer.
fcvt.fxu.trunc f8 = f8
;;
// Transfer result to GP registers.
getf.sig ret0 = f8
br.ret.sptk rp
;;
.endp __umoddi3
#endif
#ifdef L__divsi3
// Compute a 32-bit integer quotient.
//
// Use reciprocal approximation and Newton-Raphson iteration to compute the
// quotient. frcpa gives 8.6 significant bits, so we need 2 iterations
// to get more than the 32 bits of precision that we need for SImode.
//
// ??? This is currently not used. It needs to be fixed to be more like the
// above DImode routines.
//
// ??? Check to see if the error is less than >.5ulp error. We may need
// some adjustment code to get precise enough results.
//
// ??? Should probably use max precision for the reciprocal computations.
//
// r32/f8 holds the dividend. r33/f9 holds the divisor.
// f10 holds the value 2.0. f11 holds the reciprocal approximation.
// f12 is a temporary.
.text
.align 16
.global __divsi3
.proc __divsi3
__divsi3:
.regstk 2,0,0,0
setf.sig f8 = in0
setf.sig f9 = in1
;;
fcvt.xf f8 = f8
fcvt.xf f9 = f9
;;
frcpa f11, p6 = f8, f9
fadd f10 = f1, f1
;;
fnma f12 = f9, f11, f10
;;
fmpy f11 = f11, f12
;;
fnma f12 = f9, f11, f10
;;
fmpy f11 = f11, f12
;;
fmpy f8 = f8, f11
;;
fcvt.fx.trunc f8 = f8
;;
getf.sig ret0 = f8
br.ret.sptk rp
;;
.endp __divsi3
#endif
#ifdef L__modsi3
// Compute a 32-bit integer modulus.
//
// Use reciprocal approximation and Newton-Raphson iteration to compute the
// quotient. frcpa gives 8.6 significant bits, so we need 2 iterations
// to get more than the 32 bits of precision that we need for SImode.
//
// ??? This is currently not used. It needs to be fixed to be more like the
// above DImode routines.
//
// ??? Check to see if the error is less than >.5ulp error. We may need
// some adjustment code to get precise enough results.
//
// ??? Should probably use max precision for the reciprocal computations.
//
// r32/f8 holds the dividend. r33/f9 holds the divisor.
// f10 holds the value 2.0. f11 holds the reciprocal approximation.
// f12 is a temporary.
.text
.align 16
.global __modsi3
.proc __modsi3
__modsi3:
.regstk 2,0,0,0
setf.sig f8 = r32
setf.sig f9 = r33
;;
fcvt.xf f8 = f8
fcvt.xf f9 = f9
;;
frcpa f11, p6 = f8, f9
fadd f10 = f1, f1
;;
fnma f12 = f9, f11, f10
;;
fmpy f11 = f11, f12
;;
fnma f12 = f9, f11, f10
;;
fmpy f11 = f11, f12
;;
fmpy f10 = f8, f11
;;
fcvt.fx.trunc f10 = f10
;;
fcvt.xf f10 = f10
;;
fnma f8 = f10, f9, f8
;;
fcvt.fx f8 = f8
;;
getf.sig r32 = f8
br.ret.sptk rp
;;
.endp __modsi3
#endif
#ifdef L__udivsi3
// Compute a 32-bit unsigned integer quotient.
//
// Use reciprocal approximation and Newton-Raphson iteration to compute the
// quotient. frcpa gives 8.6 significant bits, so we need 2 iterations
// to get more than the 32 bits of precision that we need for SImode.
//
// ??? This is currently not used. It needs to be fixed to be more like the
// above DImode routines.
//
// ??? Check to see if the error is less than >.5ulp error. We may need
// some adjustment code to get precise enough results.
//
// ??? Should probably use max precision for the reciprocal computations.
//
// r32/f8 holds the dividend. r33/f9 holds the divisor.
// f10 holds the value 2.0. f11 holds the reciprocal approximation.
// f12 is a temporary.
//
// This is the same as divsi3, except that we don't need fcvt instructions
// before the frcpa.
.text
.align 16
.global __udivsi3
.proc __udivsi3
__udivsi3:
.regstk 2,0,0,0
setf.sig f8 = r32
setf.sig f9 = r33
;;
frcpa f11, p6 = f8, f9
fadd f10 = f1, f1
;;
fnma f12 = f9, f11, f10
;;
fmpy f11 = f11, f12
;;
fnma f12 = f9, f11, f10
;;
fmpy f11 = f11, f12
;;
fmpy f8 = f8, f11
;;
fcvt.fxu.trunc f8 = f8
;;
getf.sig ret0 = f8
br.ret.sptk rp
;;
.endp __udivsi3
#endif
#ifdef L__umodsi3
// Compute a 32-bit unsigned integer modulus.
//
// Use reciprocal approximation and Newton-Raphson iteration to compute the
// quotient. frcpa gives 8.6 significant bits, so we need 2 iterations
// to get more than the 32 bits of precision that we need for SImode.
//
// ??? This is currently not used. It needs to be fixed to be more like the
// above DImode routines.
//
// ??? Check to see if the error is less than >.5ulp error. We may need
// some adjustment code to get precise enough results.
//
// ??? Should probably use max precision for the reciprocal computations.
//
// r32/f8 holds the dividend. r33/f9 holds the divisor.
// f10 holds the value 2.0. f11 holds the reciprocal approximation.
// f12 is a temporary.
//
// This is the same as modsi3, except that we don't need fcvt instructions
// before the frcpa.
.text
.align 16
.global __umodsi3
.proc __umodsi3
__umodsi3:
.regstk 2,0,0,0
setf.sig f8 = r32
setf.sig f9 = r33
;;
frcpa f11, p6 = f8, f9
fadd f10 = f1, f1
;;
fnma f12 = f9, f11, f10
;;
fmpy f11 = f11, f12
;;
fnma f12 = f9, f11, f10
;;
fmpy f11 = f11, f12
;;
fmpy f10 = f8, f11
;;
fcvt.fxu.trunc f10 = f10
;;
fcvt.xuf f10 = f10
;;
fnma f8 = f10, f9, f8
;;
fcvt.fxu f8 = f8
;;
getf.sig r32 = f8
br.ret.sptk rp
;;
.endp __umodsi3
#endif
#ifdef L__save_stack_nonlocal
// Notes on save/restore stack nonlocal: We read ar.bsp but write
// ar.bspstore. This is because ar.bsp can be read at all times
// (independent of the RSE mode) but since it's read-only we need to
// restore the value via ar.bspstore. This is OK because
// ar.bsp==ar.bspstore after executing "flushrs".
// void __ia64_save_stack_nonlocal(void *save_area, void *stack_pointer)
.text
.align 16
.global __ia64_save_stack_nonlocal
.proc __ia64_save_stack_nonlocal
__ia64_save_stack_nonlocal:
alloc r18=ar.pfs,2,0,0,0
st8 [in0]=in1,8
mov r19=ar.rsc
;;
flushrs
and r19=0x1c,r19
mov ar.pfs=r18
;;
mov ar.rsc=r19
mov r16=ar.bsp
adds r2=16,in0
;;
mov r17=ar.rnat
st8 [in0]=r16,8
or r19=0x3,r19
;;
st8 [in0]=r17
mov ar.rsc=r19
st8 [r2]=r18
mov ar.pfs=r18
br.ret.sptk.few rp
;;
.endp __ia64_save_stack_nonlocal
#endif
#ifdef L__nonlocal_goto
// void __ia64_nonlocal_goto(void *fp, void *target_label, void *save_area,
// void *static_chain);
.text
.align 16
.global __ia64_nonlocal_goto
.proc __ia64_nonlocal_goto
__ia64_nonlocal_goto:
alloc r20=ar.pfs,4,0,0,0
mov r19=ar.rsc
adds r2=8,in2
ld8 r12=[in2],16
mov.ret.sptk.few.dc.dc rp = r33, .L0
// ??? flushrs must be first instruction of a group. Gas is unfortunately
// putting the stop bit before the padding nop instead of after it, making
// flushrs the first instruction of its bundle, but the second instruction
// of its group. We explicitly add the nop to avoid this problem.
nop.i 0
;;
flushrs
ld8 r16=[r2],16
and r19=0x1c,r19
ld8 r17=[in2]
;;
ld8 r18=[r2]
mov ar.rsc=r19
;;
mov ar.bspstore=r16
;;
mov ar.rnat=r17
mov ar.pfs=r18
or r19=0x3,r19
;;
loadrs
invala
mov r7=r32
.L0: {
mov ar.rsc=r19
mov r15=r35
br.ret.sptk.few rp
}
;;
.endp __ia64_nonlocal_goto
#endif

29
gcc/config/ia64/linux.h Normal file
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@ -0,0 +1,29 @@
/* Definitions for ia64-linux target. */
#include "ia64/ia64.h"
#include <linux.h>
#include "sysv4.h"
/* ??? Maybe this should be in sysv4.h? */
#define CPP_PREDEFINES "\
-D__ia64 -D__ia64__ -D__linux -D__linux__ -D_LONGLONG -Dlinux -Dunix \
-D__LP64__ -D__ELF__ -Asystem(linux) -Acpu(ia64) -Amachine(ia64)"
/* ??? ia64 gas doesn't accept standard svr4 assembler options? */
#undef ASM_SPEC
/* Define this for shared library support because it isn't in the main
linux.h file. */
#undef LINK_SPEC
#define LINK_SPEC "\
%{shared:-shared} \
%{!shared: \
%{!static: \
%{rdynamic:-export-dynamic} \
%{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.2}} \
%{static:-static}}"
#define DONT_USE_BUILTIN_SETJMP
#define JMP_BUF_SIZE (8 * 76)
/* End of linux.h */

248
gcc/config/ia64/sysv4.h Normal file
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@ -0,0 +1,248 @@
/* Override definitions in elfos.h/svr4.h to be correct for IA64. */
/* We want DWARF2 as specified by the IA64 ABI. */
#undef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
/* Various pseudo-ops for which the Intel assembler uses non-standard
definitions. */
#undef ASM_BYTE_OP
#define ASM_BYTE_OP "data1"
#undef STRING_ASM_OP
#define STRING_ASM_OP "stringz"
#undef SKIP_ASM_OP
#define SKIP_ASM_OP ".skip"
#undef COMMON_ASM_OP
#define COMMON_ASM_OP ".common"
#undef ASCII_DATA_ASM_OP
#define ASCII_DATA_ASM_OP "string"
/* ??? Unfortunately, .lcomm doesn't work, because it puts things in either
.bss or .sbss, and we can't control the decision of which is used. When
I use .lcomm, I get a cryptic "Section group has no member" error from
the Intel simulator. So we must explicitly put variables in .bss
instead. This matters only if we care about the Intel assembler. */
/* This is asm_output_aligned_bss from varasm.c without the ASM_GLOBALIZE_LABEL
call at the beginning. */
/* This is for final.c, because it is used by ASM_DECLARE_OBJECT_NAME. */
extern int size_directive_output;
#undef ASM_OUTPUT_ALIGNED_LOCAL
#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \
do { \
if (XSTR (XEXP (DECL_RTL (DECL), 0), 0)[0] == SDATA_NAME_FLAG_CHAR) \
sbss_section (); \
else \
bss_section (); \
ASM_OUTPUT_ALIGN (FILE, floor_log2 ((ALIGN) / BITS_PER_UNIT)); \
ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \
ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \
} while (0)
/* ??? Intel assembler does not allow "." in section names, so turn off
gnu.linkonce section support, but only when using the Intel assembler. */
#undef UNIQUE_SECTION_P
#define UNIQUE_SECTION_P(DECL) (TARGET_GNU_AS ? DECL_ONE_ONLY (DECL) : 0)
/* The # tells the Intel assembler that this is not a register name.
However, we can't emit the # in a label definition, so we set a variable
in ASM_OUTPUT_LABEL to control whether we want the postfix here or not. */
#undef ASM_OUTPUT_LABELREF
#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
do \
{ \
const char *real_name; \
STRIP_NAME_ENCODING (real_name, NAME); \
asm_fprintf (STREAM, "%U%s%s", real_name, \
(ia64_asm_output_label ? "" : "#")); \
} \
while (0)
/* Intel assembler requires both flags and type if declaring a non-predefined
section. */
#undef INIT_SECTION_ASM_OP
#define INIT_SECTION_ASM_OP ".section\t.init,\"ax\",\"progbits\""
#undef FINI_SECTION_ASM_OP
#define FINI_SECTION_ASM_OP ".section\t.fini,\"ax\",\"progbits\""
#undef CTORS_SECTION_ASM_OP
#define CTORS_SECTION_ASM_OP ".section\t.ctors,\"aw\",\"progbits\""
#undef DTORS_SECTION_ASM_OP
#define DTORS_SECTION_ASM_OP ".section\t.dtors,\"aw\",\"progbits\""
/* A C statement (sans semicolon) to output an element in the table of
global constructors. */
/* Must override this to get @fptr relocation. */
#undef ASM_OUTPUT_CONSTRUCTOR
#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
do { \
ctors_section (); \
fputs ("\tdata8\t @fptr(", FILE); \
assemble_name (FILE, NAME); \
fputs (")\n", FILE); \
} while (0)
/* A C statement (sans semicolon) to output an element in the table of
global destructors. */
/* Must override this to get @fptr relocation. */
#undef ASM_OUTPUT_DESTRUCTOR
#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
do { \
dtors_section (); \
fputs ("\tdata8\t @fptr(", FILE); \
assemble_name (FILE, NAME); \
fputs (")\n", FILE); \
} while (0)
/* svr4.h undefines this, so we need to define it here. */
#define DBX_REGISTER_NUMBER(REGNO) \
(IN_REGNO_P (REGNO) ? (32 + (REGNO) - IN_REG (0)) \
: LOC_REGNO_P (REGNO) ? (32 + ia64_input_regs + \
(REGNO) - LOC_REG (0)) \
: OUT_REGNO_P (REGNO) ? (32 + ia64_input_regs + ia64_local_regs \
+ (REGNO) - OUT_REG (0)) \
: (REGNO) == FRAME_POINTER_REGNUM ? ia64_fp_regno \
: (REGNO))
/* Things that svr4.h defines to the wrong type, because it assumes 32 bit
ints and 32 bit longs. */
#undef SIZE_TYPE
#define SIZE_TYPE "long unsigned int"
#undef PTRDIFF_TYPE
#define PTRDIFF_TYPE "long int"
#undef WCHAR_TYPE
#define WCHAR_TYPE "int"
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE 32
/* We don't want any symbol at the beginning of the file. This is defined in
dbxelf.h which is included from elfos.h, so we need to undef/define it
here. */
#undef ASM_IDENTIFY_GCC
#define ASM_IDENTIFY_GCC(FILE)
/* We redefine this to use the ia64 .proc pseudo-op. */
#undef ASM_DECLARE_FUNCTION_NAME
#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
do { \
fputs ("\t.proc ", FILE); \
assemble_name (FILE, NAME); \
fputc ('\n', FILE); \
ASM_OUTPUT_LABEL (FILE, NAME); \
} while (0)
/* We redefine this to use the ia64 .endp pseudo-op. */
#undef ASM_DECLARE_FUNCTION_SIZE
#define ASM_DECLARE_FUNCTION_SIZE(FILE, NAME, DECL) \
do { \
fputs ("\t.endp ", FILE); \
assemble_name (FILE, NAME); \
fputc ('\n', FILE); \
} while (0)
/* A C expression which outputs to the stdio stream STREAM some appropriate
text to go at the start of an assembler file. */
/* ??? Looks like almost every port, except for a few original ones, get this
wrong. Must emit #NO_APP as first line of file to turn of special assembler
preprocessing of files. */
/* ??? Even worse, it doesn't work, because gas does not accept the tab chars
that dwarf2out.c emits when #NO_APP. */
/* ??? Unrelated, but dwarf2out.c emits unnecessary newlines after strings,
may as well fix at the same time. */
#if 0
#undef ASM_FILE_START
#define ASM_FILE_START(STREAM) \
do { \
fputs (ASM_APP_OFF, STREAM); \
output_file_directive (STREAM, main_input_filename); \
} while (0)
#endif
/* Case label alignment is handled by ADDR_VEC_ALIGN now. */
#undef ASM_OUTPUT_BEFORE_CASE_LABEL
#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE)
/* We override svr4.h so that we can support the sdata section. */
#undef SELECT_SECTION
#define SELECT_SECTION(DECL,RELOC) \
{ \
if (TREE_CODE (DECL) == STRING_CST) \
{ \
if (! flag_writable_strings) \
const_section (); \
else \
data_section (); \
} \
else if (TREE_CODE (DECL) == VAR_DECL) \
{ \
if (XSTR (XEXP (DECL_RTL (DECL), 0), 0)[0] \
== SDATA_NAME_FLAG_CHAR) \
sdata_section (); \
/* ??? We need the extra ! RELOC check, because the default is to \
only check RELOC if flag_pic is set, and we don't set flag_pic \
(yet?). */ \
else if (DECL_READONLY_SECTION (DECL, RELOC) && ! (RELOC)) \
const_section (); \
else \
data_section (); \
} \
else \
const_section (); \
}
#undef EXTRA_SECTIONS
#define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_sdata, in_sbss
#undef EXTRA_SECTION_FUNCTIONS
#define EXTRA_SECTION_FUNCTIONS \
CONST_SECTION_FUNCTION \
CTORS_SECTION_FUNCTION \
DTORS_SECTION_FUNCTION \
SDATA_SECTION_FUNCTION \
SBSS_SECTION_FUNCTION
#define SDATA_SECTION_ASM_OP ".sdata"
#define SDATA_SECTION_FUNCTION \
void \
sdata_section () \
{ \
if (in_section != in_sdata) \
{ \
fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
in_section = in_sdata; \
} \
}
#define SBSS_SECTION_ASM_OP ".sbss"
#define SBSS_SECTION_FUNCTION \
void \
sbss_section () \
{ \
if (in_section != in_sbss) \
{ \
fprintf (asm_out_file, "%s\n", SBSS_SECTION_ASM_OP); \
in_section = in_sbss; \
} \
}

41
gcc/config/ia64/t-ia64 Normal file
View File

@ -0,0 +1,41 @@
# Name of assembly file containing libgcc1 functions.
# This entry must be present, but it can be empty if the target does
# not need any assembler functions to support its code generation.
CROSS_LIBGCC1 = libgcc1-asm.a
LIBGCC1 = libgcc1-asm.a
LIB1ASMSRC = ia64/lib1funcs.asm
# ??? We change the names of the DImode div/mod files so that they won't
# accidentally be overridden by libgcc2.c files. We used to use __ia64 as
# a prefix, now we use __ as the prefix.
LIB1ASMFUNCS = __divdf3 __divsf3 \
__divdi3 __moddi3 __udivdi3 __umoddi3 \
__divsi3 __modsi3 __udivsi3 __umodsi3 __save_stack_nonlocal \
__nonlocal_goto
# ??? Hack to get -P option used when compiling lib1funcs.asm, because Intel
# assembler does not accept # line number as a comment.
# ??? This breaks C++ pragma interface/implementation, which is used in the
# C++ part of libgcc2, hence it had to be disabled. Must find some other way
# to support the Intel assembler.
#LIBGCC2_DEBUG_CFLAGS = -g1 -P
# For svr4 we build crtbegin.o and crtend.o which serve to add begin and
# end labels to the .ctors and .dtors section when we link using gcc.
EXTRA_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o
# Effectively disable the crtbegin/end rules using crtstuff.c
T = disable
# Assemble startup files.
crtbegin.o: $(srcdir)/config/ia64/crtbegin.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) -c -o crtbegin.o -x assembler-with-cpp $(srcdir)/config/ia64/crtbegin.asm
crtend.o: $(srcdir)/config/ia64/crtend.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) -c -o crtend.o -x assembler-with-cpp $(srcdir)/config/ia64/crtend.asm
crtbeginS.o: $(srcdir)/config/ia64/crtbegin.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) -DSHARED -c -o crtbeginS.o -x assembler-with-cpp $(srcdir)/config/ia64/crtbegin.asm
crtendS.o: $(srcdir)/config/ia64/crtend.asm $(GCC_PASSES)
$(GCC_FOR_TARGET) -DSHARED -c -o crtendS.o -x assembler-with-cpp $(srcdir)/config/ia64/crtend.asm
EXTRA_HEADERS = $(srcdir)/config/ia64/ia64intrin.h

61
gcc/config/ia64/xm-ia64.h Normal file
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@ -0,0 +1,61 @@
/* Definitions of target machine for IA64.
Copyright (C) 1999 Cygnus Solutions.
This file is part of GNU CC.
GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
/* #defines that need visibility everywhere. */
#define FALSE 0
#define TRUE 1
/* A C expression for the status code to be returned when the compiler exits
after serious errors. */
#define FATAL_EXIT_CODE 33
/* A C expression for the status code to be returned when the compiler exits
without serious errors. */
#define SUCCESS_EXIT_CODE 0
/* Defined if the host machine stores words of multi-word values in big-endian
order. (GNU CC does not depend on the host byte ordering within a word.) */
#ifdef __BIG_ENDIAN__
#define HOST_WORDS_BIG_ENDIAN
#endif
/* A C expression for the number of bits in `char' on the host machine. */
#define HOST_BITS_PER_CHAR 8
/* A C expression for the number of bits in `short' on the host machine. */
#define HOST_BITS_PER_SHORT 16
/* A C expression for the number of bits in `int' on the host machine. */
#define HOST_BITS_PER_INT 32
/* ??? This depends on the as yet unimplemented ILP32 option. */
/* A C expression for the number of bits in `long' on the host machine. */
#define HOST_BITS_PER_LONG 64
/* A C expression for the number of bits in `long long' on the host
machine. */
#define HOST_BITS_PER_LONGLONG 64
/* target machine dependencies.
tm.h is a symbolic link to the actual target specific file. */
#include "tm.h"
/* end of xm-ia64.h */

21
gcc/configure vendored
View File

@ -4489,6 +4489,27 @@ for machine in $build $host $target; do
i960-*-*) # Default i960 environment.
use_collect2=yes
;;
ia64*-*-elf*)
tm_file=ia64/elf.h
tmake_file="ia64/t-ia64"
target_cpu_default="0"
if test x$gas = xyes
then
target_cpu_default="${target_cpu_default}|MASK_GNU_AS"
fi
if test x$gnu_ld = xyes
then
target_cpu_default="${target_cpu_default}|MASK_GNU_LD"
fi
;;
ia64*-*-linux*)
tm_file=ia64/linux.h
tmake_file="t-linux ia64/t-ia64"
target_cpu_default="MASK_GNU_AS|MASK_GNU_LD"
if test x$enable_threads = xyes; then
thread_file='posix'
fi
;;
m32r-*-elf*)
extra_parts="crtinit.o crtfini.o"
;;

21
gcc/configure.in
View File

@ -1859,6 +1859,27 @@ changequote([,])dnl
i960-*-*) # Default i960 environment.
use_collect2=yes
;;
ia64*-*-elf*)
tm_file=ia64/elf.h
tmake_file="ia64/t-ia64"
target_cpu_default="0"
if test x$gas = xyes
then
target_cpu_default="${target_cpu_default}|MASK_GNU_AS"
fi
if test x$gnu_ld = xyes
then
target_cpu_default="${target_cpu_default}|MASK_GNU_LD"
fi
;;
ia64*-*-linux*)
tm_file=ia64/linux.h
tmake_file="t-linux ia64/t-ia64"
target_cpu_default="MASK_GNU_AS|MASK_GNU_LD"
if test x$enable_threads = xyes; then
thread_file='posix'
fi
;;
m32r-*-elf*)
extra_parts="crtinit.o crtfini.o"
;;