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Support avx512f in __builtin_cpu_supports.
gcc/ * config/i386/cpuid.h (bit_MPX, bit_BNDREGS, bit_BNDCSR): Define. * config/i386/i386.c (get_builtin_code_for_version): Add avx512f. (fold_builtin_cpu): Ditto. * doc/extend.texi: Documment it. gcc/testsuite/ * g++.dg/ext/mv2.C: Add test for target ("avx512f"). * gcc.target/i386/builtin_target.c: Ditto. libgcc/ * config/i386/cpuinfo.c (processor_features): Add FEATURE_AVX512F. * config/i386/cpuinfo.c (get_available_features): Detect it. From-SVN: r218125
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@ -1,3 +1,11 @@
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2014-11-27 Ilya Tocar <ilya.tocar@intel.com>
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* config/i386/cpuid.h (bit_MPX, bit_BNDREGS, bit_BNDCSR):
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Define.
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* config/i386/i386.c (get_builtin_code_for_version): Add avx512f.
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(fold_builtin_cpu): Ditto.
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* doc/extend.texi: Documment it.
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2014-11-27 Jakub Jelinek <jakub@redhat.com>
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PR middle-end/64067
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@ -72,6 +72,7 @@
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#define bit_AVX2 (1 << 5)
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#define bit_BMI2 (1 << 8)
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#define bit_RTM (1 << 11)
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#define bit_MPX (1 << 14)
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#define bit_AVX512F (1 << 16)
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#define bit_AVX512DQ (1 << 17)
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#define bit_RDSEED (1 << 18)
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@ -91,6 +92,10 @@
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#define bit_PREFETCHWT1 (1 << 0)
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#define bit_AVX512VBMI (1 << 1)
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/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
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#define bit_BNDREGS (1 << 3)
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#define bit_BNDCSR (1 << 4)
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/* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
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#define bit_XSAVEOPT (1 << 0)
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#define bit_XSAVEC (1 << 1)
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@ -34235,7 +34235,8 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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P_FMA,
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P_PROC_FMA,
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P_AVX2,
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P_PROC_AVX2
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P_PROC_AVX2,
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P_AVX512F
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};
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enum feature_priority priority = P_ZERO;
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@ -34263,7 +34264,8 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
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{"fma4", P_FMA4},
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{"xop", P_XOP},
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{"fma", P_FMA},
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{"avx2", P_AVX2}
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{"avx2", P_AVX2},
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{"avx512f", P_AVX512F}
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};
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@ -35238,6 +35240,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
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F_FMA4,
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F_XOP,
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F_FMA,
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F_AVX512F,
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F_MAX
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};
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@ -35326,7 +35329,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
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{"fma4", F_FMA4},
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{"xop", F_XOP},
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{"fma", F_FMA},
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{"avx2", F_AVX2}
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{"avx2", F_AVX2},
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{"avx512f",F_AVX512F}
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};
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tree __processor_model_type = build_processor_model_struct ();
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@ -11642,6 +11642,8 @@ SSE4.2 instructions.
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AVX instructions.
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@item avx2
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AVX2 instructions.
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@item avx512f
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AVX512F instructions.
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@end table
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Here is an example:
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@ -1,3 +1,8 @@
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2014-11-27 Ilya Tocar <ilya.tocar@intel.com>
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* g++.dg/ext/mv2.C: Add test for target ("avx512f").
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* gcc.target/i386/builtin_target.c: Ditto.
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2014-11-27 Kai Tietz <ktietz@redhat.com>
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PR c++/63904
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@ -20,31 +20,34 @@ int foo () __attribute__ ((target ("sse4.2")));
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int foo () __attribute__ ((target ("popcnt")));
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int foo () __attribute__ ((target ("avx")));
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int foo () __attribute__ ((target ("avx2")));
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int foo () __attribute__ ((target ("avx512f")));
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int main ()
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{
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int val = foo ();
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if (__builtin_cpu_supports ("avx2"))
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assert (val == 1);
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else if (__builtin_cpu_supports ("avx"))
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assert (val == 2);
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else if (__builtin_cpu_supports ("popcnt"))
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assert (val == 3);
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else if (__builtin_cpu_supports ("sse4.2"))
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assert (val == 4);
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else if (__builtin_cpu_supports ("sse4.1"))
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assert (val == 5);
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else if (__builtin_cpu_supports ("ssse3"))
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assert (val == 6);
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else if (__builtin_cpu_supports ("sse3"))
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assert (val == 7);
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else if (__builtin_cpu_supports ("sse2"))
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assert (val == 8);
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else if (__builtin_cpu_supports ("sse"))
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assert (val == 9);
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else if (__builtin_cpu_supports ("mmx"))
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if (__builtin_cpu_supports ("avx512f"))
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assert (val == 11);
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else if (__builtin_cpu_supports ("avx2"))
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assert (val == 10);
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else if (__builtin_cpu_supports ("avx"))
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assert (val == 9);
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else if (__builtin_cpu_supports ("popcnt"))
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assert (val == 8);
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else if (__builtin_cpu_supports ("sse4.2"))
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assert (val == 7);
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else if (__builtin_cpu_supports ("sse4.1"))
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assert (val == 6);
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else if (__builtin_cpu_supports ("ssse3"))
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assert (val == 5);
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else if (__builtin_cpu_supports ("sse3"))
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assert (val == 4);
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else if (__builtin_cpu_supports ("sse2"))
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assert (val == 3);
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else if (__builtin_cpu_supports ("sse"))
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assert (val == 2);
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else if (__builtin_cpu_supports ("mmx"))
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assert (val == 1);
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else
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assert (val == 0);
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@ -60,59 +63,65 @@ foo ()
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int __attribute__ ((target("mmx")))
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foo ()
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{
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return 10;
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return 1;
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}
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int __attribute__ ((target("sse")))
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foo ()
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{
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return 9;
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return 2;
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}
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int __attribute__ ((target("sse2")))
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foo ()
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{
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return 8;
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return 3;
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}
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int __attribute__ ((target("sse3")))
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foo ()
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{
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return 7;
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return 4;
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}
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int __attribute__ ((target("ssse3")))
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foo ()
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{
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return 6;
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return 5;
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}
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int __attribute__ ((target("sse4.1")))
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foo ()
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{
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return 5;
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return 6;
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}
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int __attribute__ ((target("sse4.2")))
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foo ()
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{
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return 4;
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return 7;
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}
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int __attribute__ ((target("popcnt")))
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foo ()
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{
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return 3;
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return 8;
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}
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int __attribute__ ((target("avx")))
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foo ()
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{
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return 2;
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return 9;
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}
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int __attribute__ ((target("avx2")))
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foo ()
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{
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return 1;
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return 10;
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}
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int __attribute__ ((target("avx512f")))
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foo ()
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{
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return 11;
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}
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@ -145,6 +145,8 @@ check_features (unsigned int ecx, unsigned int edx,
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__cpuid_count (7, 0, eax, ebx, ecx, edx);
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if (ebx & bit_AVX2)
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assert (__builtin_cpu_supports ("avx2"));
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if (ebx & bit_AVX512F)
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assert (__builtin_cpu_supports ("avx512f"));
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}
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}
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@ -241,6 +243,8 @@ quick_check ()
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assert (__builtin_cpu_supports ("avx2") >= 0);
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assert (__builtin_cpu_supports ("avx512f") >= 0);
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/* Check CPU type. */
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assert (__builtin_cpu_is ("amd") >= 0);
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@ -1,3 +1,8 @@
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2014-11-27 Ilya Tocar <ilya.tocar@intel.com>
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* config/i386/cpuinfo.c (processor_features): Add FEATURE_AVX512F.
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* config/i386/cpuinfo.c (get_available_features): Detect it.
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2014-11-27 Tony Wang <tony.wang@arm.com>
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* config/arm/lib1funcs.S (FUNC_START): Add conditional section
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@ -96,7 +96,8 @@ enum processor_features
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FEATURE_SSE4_A,
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FEATURE_FMA4,
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FEATURE_XOP,
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FEATURE_FMA
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FEATURE_FMA,
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FEATURE_AVX512F
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};
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struct __processor_model
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@ -278,6 +279,8 @@ get_available_features (unsigned int ecx, unsigned int edx,
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__cpuid_count (7, 0, eax, ebx, ecx, edx);
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if (ebx & bit_AVX2)
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features |= (1 << FEATURE_AVX2);
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if (ebx & bit_AVX512F)
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features |= (1 << FEATURE_AVX512F);
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}
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unsigned int ext_level;
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