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irix-csr.c: New file.

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* config/mips/irix-csr.c: New file.
	* config/mips/t-iris6 (irix-csr.o): New rule to build it.
	(EXTRA_MULTILIB_PARTS): Add irix-csr.o.
	* config/mips/iris6.h (ENDFILE_SPEC): Include it in n32 and n64
	executables.

From-SVN: r94186
This commit is contained in:
Richard Sandiford 2005-01-24 21:42:50 +00:00 committed by Richard Sandiford
parent 81b4721953
commit c0fd73a9ad
4 changed files with 33 additions and 1 deletions
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8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2005-01-24 Richard Sandiford <rsandifo@redhat.com>
* config/mips/irix-csr.c: New file.
* config/mips/t-iris6 (irix-csr.o): New rule to build it.
(EXTRA_MULTILIB_PARTS): Add irix-csr.o.
* config/mips/iris6.h (ENDFILE_SPEC): Include it in n32 and n64
executables.
2005-01-24 Eric Botcazou <ebotcazou@libertysurf.fr>
PR bootstrap/19364

3
gcc/config/mips/iris6.h
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@ -97,7 +97,8 @@ Boston, MA 02111-1307, USA. */
#undef ENDFILE_SPEC
#define ENDFILE_SPEC \
"crtend.o%s irix-crtn.o%s \
"%{!shared:%{mabi=n32|mabi=64:irix-csr.o%s}} \
crtend.o%s irix-crtn.o%s \
%{!shared: \
%{mabi=32:crtn.o%s}\
%{mabi=n32:%{mips4:/usr/lib32/mips4/crtn.o%s}\

17
gcc/config/mips/irix-csr.c Normal file
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@ -0,0 +1,17 @@
#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
#include <sys/fpu.h>
/* n32 and n64 applications usually run with the MIPS IV Flush to Zero
bit set. Clear it here so that gcc-generated code will handle
subnormals correctly by default. */
static void __attribute__((constructor))
clear_flush_to_zero (void)
{
union fpc_csr csr;
csr.fc_word = get_fpc_csr ();
csr.fc_struct.flush = 0;
set_fpc_csr (csr.fc_word);
}
#endif

6
gcc/config/mips/t-iris6
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@ -19,3 +19,9 @@ tp-bit.c: $(srcdir)/config/fp-bit.c
echo '# define TFLOAT' >> tp-bit.c
cat $(srcdir)/config/fp-bit.c >> tp-bit.c
echo '#endif' >> tp-bit.c
$(T)irix-csr.o: $(srcdir)/config/mips/irix-csr.c $(GCC_PASSES)
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
-c -o $@ $<
EXTRA_MULTILIB_PARTS += irix-csr.o