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[AArch64] Catch attempts to use SVE types when SVE is disabled

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This patch reports an error if code tries to use variable-length
SVE types when SVE is disabled.  We already report a similar error
for definitions or uses of SVE functions when SVE is disabled.

2019-12-02  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_report_sve_required): New function.
	(aarch64_expand_mov_immediate): Use it when attempting to measure
	the length of an SVE vector.
	(aarch64_mov_operand_p): Only allow SVE CNT immediates when
	SVE is enabled.

gcc/testsuite/
	* gcc.target/aarch64/sve/acle/general/nosve_4.c: New test.
	* gcc.target/aarch64/sve/acle/general/nosve_5.c: Likewise.
	* gcc.target/aarch64/sve/pcs/nosve_4.c: Expected a second error
	for the copy.
	* gcc.target/aarch64/sve/pcs/nosve_5.c: Likewise.
	* gcc.target/aarch64/sve/pcs/nosve_6.c: Likewise.

From-SVN: r278909
This commit is contained in:
Richard Sandiford 2019-12-02 17:48:08 +00:00 committed by Richard Sandiford
parent 6da4c454ac
commit c0e0174bbd
8 changed files with 64 additions and 4 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2019-12-02 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.c (aarch64_report_sve_required): New function.
(aarch64_expand_mov_immediate): Use it when attempting to measure
the length of an SVE vector.
(aarch64_mov_operand_p): Only allow SVE CNT immediates when
SVE is enabled.
2019-12-02 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-sve-builtins.h

26
gcc/config/aarch64/aarch64.c
View File

@ -1473,6 +1473,25 @@ aarch64_err_no_fpadvsimd (machine_mode mode)
" vector types", "+nofp");
}
/* Report when we try to do something that requires SVE when SVE is disabled.
This is an error of last resort and isn't very high-quality. It usually
involves attempts to measure the vector length in some way. */
static void
aarch64_report_sve_required (void)
{
static bool reported_p = false;
/* Avoid reporting a slew of messages for a single oversight. */
if (reported_p)
return;
error ("this operation requires the SVE ISA extension");
inform (input_location, "you can enable SVE using the command-line"
" option %<-march%>, or by using the %<target%>"
" attribute or pragma");
reported_p = true;
}
/* Return true if REGNO is P0-P15 or one of the special FFR-related
registers. */
inline bool
@ -4525,6 +4544,11 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
folding it into the relocation. */
if (!offset.is_constant (&const_offset))
{
if (!TARGET_SVE)
{
aarch64_report_sve_required ();
return;
}
if (base == const0_rtx && aarch64_sve_cnt_immediate_p (offset))
emit_insn (gen_rtx_SET (dest, imm));
else
@ -16864,7 +16888,7 @@ aarch64_mov_operand_p (rtx x, machine_mode mode)
if (GET_CODE (x) == SYMBOL_REF && mode == DImode && CONSTANT_ADDRESS_P (x))
return true;
if (aarch64_sve_cnt_immediate_p (x))
if (TARGET_SVE && aarch64_sve_cnt_immediate_p (x))
return true;
return aarch64_classify_symbolic_expression (x)

9
gcc/testsuite/ChangeLog
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@ -1,3 +1,12 @@
2019-12-02 Richard Sandiford <richard.sandiford@arm.com>
* gcc.target/aarch64/sve/acle/general/nosve_4.c: New test.
* gcc.target/aarch64/sve/acle/general/nosve_5.c: Likewise.
* gcc.target/aarch64/sve/pcs/nosve_4.c: Expected a second error
for the copy.
* gcc.target/aarch64/sve/pcs/nosve_5.c: Likewise.
* gcc.target/aarch64/sve/pcs/nosve_6.c: Likewise.
2019-12-02 Richard Sandiford <richard.sandiford@arm.com>
* gcc.target/aarch64/sve/acle/aarch64-sve-acle.exp: Run the

8
gcc/testsuite/gcc.target/aarch64/sve/acle/general/nosve_4.c Normal file
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@ -0,0 +1,8 @@
/* { dg-options "-march=armv8-a" } */
void
f (__SVBool_t *x, __SVBool_t *y)
{
*x = *y; /* { dg-error {this operation requires the SVE ISA extension} } */
*x = *y;
}

8
gcc/testsuite/gcc.target/aarch64/sve/acle/general/nosve_5.c Normal file
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@ -0,0 +1,8 @@
/* { dg-options "-march=armv8-a" } */
void
f (__SVInt8_t *x, __SVInt8_t *y)
{
*x = *y; /* { dg-error {this operation requires the SVE ISA extension} } */
*x = *y;
}

3
gcc/testsuite/gcc.target/aarch64/sve/pcs/nosve_4.c
View File

@ -10,5 +10,6 @@ void take_svuint8 (svuint8_t);
void
f (svuint8_t *ptr)
{
take_svuint8 (*ptr); /* { dg-error {'take_svuint8' requires the SVE ISA extension} } */
take_svuint8 (*ptr); /* { dg-error {this operation requires the SVE ISA extension} } */
/* { dg-error {'take_svuint8' requires the SVE ISA extension} "" { target *-*-* } .-1 } */
}

3
gcc/testsuite/gcc.target/aarch64/sve/pcs/nosve_5.c
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@ -11,5 +11,6 @@ void take_svuint8_eventually (float, float, float, float,
void
f (svuint8_t *ptr)
{
take_svuint8_eventually (0, 0, 0, 0, 0, 0, 0, 0, *ptr); /* { dg-error {arguments of type '(svuint8_t|__SVUint8_t)' require the SVE ISA extension} } */
take_svuint8_eventually (0, 0, 0, 0, 0, 0, 0, 0, *ptr); /* { dg-error {this operation requires the SVE ISA extension} } */
/* { dg-error {arguments of type '(svuint8_t|__SVUint8_t)' require the SVE ISA extension} "" { target *-*-* } .-1 } */
}

3
gcc/testsuite/gcc.target/aarch64/sve/pcs/nosve_6.c
View File

@ -10,5 +10,6 @@ void unprototyped ();
void
f (svuint8_t *ptr)
{
unprototyped (*ptr); /* { dg-error {arguments of type '(svuint8_t|__SVUint8_t)' require the SVE ISA extension} } */
unprototyped (*ptr); /* { dg-error {this operation requires the SVE ISA extension} } */
/* { dg-error {arguments of type '(svuint8_t|__SVUint8_t)' require the SVE ISA extension} "" { target *-*-* } .-1 } */
}