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re PR target/65561 (avx512fintrin.h:5344:1: internal compiler error: in curr_insn_transform, at lra-constraints.c:3494)

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PR target/65561
	* config/i386/sse.md (avx512dq_vextract<shuffletype>64x2_1_maskm):
	Check operand 4 and operand 0 for equality.
	(avx512f_vextract<shuffletype>32x4_1_maskm):
	Check operand 6 and operand 0 for equality.
	(vec_extract_lo_<mode>_maskm): Check operand 2 and operand 0
	for equality.
	(vec_extract_hi_<mode>_maskm): Ditto.

From-SVN: r221709
This commit is contained in:
Uros Bizjak 2015-03-26 21:37:53 +01:00
parent d1a74a287e
commit bf3b2de71f
2 changed files with 29 additions and 14 deletions
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16
gcc/ChangeLog
View File

@ -1,3 +1,14 @@
2015-03-26 Uros Bizjak <ubizjak@gmail.com>
PR target/65561
* config/i386/sse.md (avx512dq_vextract<shuffletype>64x2_1_maskm):
Check operand 4 and operand 0 for equality.
(avx512f_vextract<shuffletype>32x4_1_maskm):
Check operand 6 and operand 0 for equality.
(vec_extract_lo_<mode>_maskm): Check operand 2 and operand 0
for equality.
(vec_extract_hi_<mode>_maskm): Ditto.
2015-03-26 Jan Hubicka <hubicka@ucw.cz>
* cgraph.c (cgraph_update_edges_for_call_stmt_node): Do not bring
@ -17,7 +28,7 @@
(compute_inline_parameters): Compute contains_cilk_spawn.
(inline_read_section, inline_write_summary): Stream
contains_cilk_spawn.
* ipa-inline.c (can_inline_edge_p): Do not tuch
* ipa-inline.c (can_inline_edge_p): Do not touch
DECL_STRUCT_FUNCTION that may not be available;
use CIF_CILK_SPAWN for cilk; fix optimization attribute checks;
remove check for callee_fun->can_throw_non_call_exceptions and
@ -41,8 +52,7 @@
2015-03-26 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/64715
* passes.def: Add another instance of pass_object_sizes before
ccp1.
* passes.def: Add another instance of pass_object_sizes before ccp1.
* tree-object-size.c (pass_object_sizes::execute): In
first_pass_instance, only handle __bos (, 1) and __bos (, 3)
calls, and keep the call in the IL, as {MIN,MAX}_EXPR of the

27
gcc/config/i386/sse.md
View File

@ -6633,7 +6633,8 @@
(match_operand:QI 5 "register_operand" "k")))]
"TARGET_AVX512DQ
&& (INTVAL (operands[2]) % 2 == 0)
&& (INTVAL (operands[2]) == INTVAL (operands[3]) - 1 )"
&& (INTVAL (operands[2]) == INTVAL (operands[3]) - 1)
&& rtx_equal_p (operands[4], operands[0])"
{
operands[2] = GEN_INT ((INTVAL (operands[2])) >> 1);
return "vextract<shuffletype>64x2\t{%2, %1, %0%{%5%}|%0%{%5%}, %1, %2}";
@ -6660,7 +6661,8 @@
&& ((INTVAL (operands[2]) % 4 == 0)
&& INTVAL (operands[2]) == (INTVAL (operands[3]) - 1)
&& INTVAL (operands[3]) == (INTVAL (operands[4]) - 1)
&& INTVAL (operands[4]) == (INTVAL (operands[5]) - 1))"
&& INTVAL (operands[4]) == (INTVAL (operands[5]) - 1))
&& rtx_equal_p (operands[6], operands[0])"
{
operands[2] = GEN_INT ((INTVAL (operands[2])) >> 2);
return "vextract<shuffletype>32x4\t{%2, %1, %0%{%7%}|%0%{%7%}, %1, %2}";
@ -6777,7 +6779,8 @@
(const_int 2) (const_int 3)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:QI 3 "register_operand" "Yk")))]
"TARGET_AVX512F"
"TARGET_AVX512F
&& rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>64x4\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
@ -6813,7 +6816,8 @@
(const_int 6) (const_int 7)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:QI 3 "register_operand" "Yk")))]
"TARGET_AVX512F"
"TARGET_AVX512F
&& rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>64x4\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
[(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
@ -6847,7 +6851,8 @@
(const_int 14) (const_int 15)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:QI 3 "register_operand" "k")))]
"TARGET_AVX512DQ"
"TARGET_AVX512DQ
&& rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>32x8\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
@ -7071,8 +7076,9 @@
(const_int 2) (const_int 3)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:QI 3 "register_operand" "k")))]
"TARGET_AVX512VL && TARGET_AVX512F"
"vextract<shuffletype>32x4\t{$0x0, %1, %0%{3%}|%0%{%3%}, %1, 0x0}"
"TARGET_AVX512VL && TARGET_AVX512F
&& rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>32x4\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
@ -7088,10 +7094,9 @@
(const_int 6) (const_int 7)]))
(match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
(match_operand:<ssehalfvecmode> 3 "register_operand" "k")))]
"TARGET_AVX512F && TARGET_AVX512VL"
{
return "vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}";
}
"TARGET_AVX512F && TARGET_AVX512VL
&& rtx_equal_p (operands[2], operands[0])"
"vextract<shuffletype>32x4\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
[(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")