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alpha.c (alpha_cpu_name): New variable.
* alpha.c (alpha_cpu_name): New variable. (alpha_mlat_string): Likewise. (alpha_memory_latency): Likewise. (override_options): Handle -mmemory-latency. (alpha_adjust_cost): Adjust load cost for latency. * alpha.h (TARGET_OPTIONS): Add meory-latency. (REGISTER_MOVE_COST): Define in terms of memory_latency. Take TARGET_CIX into account. (MEMORY_MOVE_COST): Define in terms of memory_latency. * invoke.texi (DEC Alpha Options): Document -mmemory-latency. * alpha.h (ASM_COMMENT_START): New macro. From-SVN: r17106
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Richard Henderson
Richard Henderson
parent
1914f5da24
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bcbbac264c
@ -1,4 +1,19 @@
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Mon Dec 15 17:48:05 1997 Ricahrd Henderson <rth@cygnus.com>
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Mon Dec 15 18:31:43 1997 Richard Henderson <rth@cygnus.com>
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* alpha.c (alpha_cpu_name): New variable.
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(alpha_mlat_string): Likewise.
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(alpha_memory_latency): Likewise.
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(override_options): Handle -mmemory-latency.
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(alpha_adjust_cost): Adjust load cost for latency.
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* alpha.h (TARGET_OPTIONS): Add meory-latency.
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(REGISTER_MOVE_COST): Define in terms of memory_latency. Take
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TARGET_CIX into account.
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(MEMORY_MOVE_COST): Define in terms of memory_latency.
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* invoke.texi (DEC Alpha Options): Document -mmemory-latency.
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* alpha.h (ASM_COMMENT_START): New macro.
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Mon Dec 15 17:48:05 1997 Richard Henderson <rth@cygnus.com>
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* reload.h, reload1.c (eliminate_regs), caller-save.c, dbxout.c,
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dwarfout.c, dwarf2out.c, reload.c, sdbout.c: Revert March 15 change.
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@ -22,6 +22,7 @@ Boston, MA 02111-1307, USA. */
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#include "config.h"
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#include <stdio.h>
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#include <ctype.h>
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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@ -47,6 +48,10 @@ extern int rtx_equal_function_value_matters;
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/* Specify which cpu to schedule for. */
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enum processor_type alpha_cpu;
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static char* const alpha_cpu_name[] =
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{
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"ev4", "ev5", "ev6"
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};
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/* Specify how accurate floating-point traps need to be. */
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@ -62,10 +67,11 @@ enum alpha_fp_trap_mode alpha_fptm;
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/* Strings decoded into the above options. */
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char *alpha_cpu_string; /* -mcpu=ev[4|5] */
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char *alpha_cpu_string; /* -mcpu= */
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char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
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char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
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char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
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char *alpha_mlat_string; /* -mmemory-latency= */
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/* Save information from a "cmpxx" operation until the branch or scc is
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emitted. */
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@ -91,6 +97,10 @@ int alpha_function_needs_gp;
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static rtx alpha_return_addr_rtx;
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/* The number of cycles of latency we should assume on memory reads. */
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int alpha_memory_latency = 3;
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/* Declarations of static functions. */
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static void alpha_set_memflags_1 PROTO((rtx, int, int, int));
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static rtx alpha_emit_set_const_1 PROTO((rtx, enum machine_mode,
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@ -243,6 +253,52 @@ override_options ()
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alpha_fptm = ALPHA_FPTM_SU;
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}
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}
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{
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char *end;
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int lat;
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if (!alpha_mlat_string)
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alpha_mlat_string = "L1";
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if (isdigit (alpha_mlat_string[0])
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&& (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
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;
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else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
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&& isdigit (alpha_mlat_string[1])
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&& alpha_mlat_string[2] == '\0')
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{
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static int const cache_latency[][4] =
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{
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{ 3, 30, -1 }, /* ev4 -- Bcache is a guess */
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{ 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
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{ 3, 12, -1 }, /* ev6 -- Ho hum, doesn't exist yet */
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};
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lat = alpha_mlat_string[1] - '0';
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if (lat < 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
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{
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warning ("L%d cache latency unknown for %s",
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lat, alpha_cpu_name[alpha_cpu]);
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lat = 3;
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}
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else
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lat = cache_latency[alpha_cpu][lat-1];
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}
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else if (! strcmp (alpha_mlat_string, "main"))
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{
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/* Most current memories have about 370ns latency. This is
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a reasonable guess for a fast cpu. */
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lat = 150;
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}
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else
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{
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warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
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lat = 3;
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}
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alpha_memory_latency = lat;
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}
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}
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/* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
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@ -1217,6 +1273,10 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
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insn_type = get_attr_type (insn);
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dep_insn_type = get_attr_type (dep_insn);
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/* Bring in the user-defined memory latency. */
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if (dep_insn_type == TYPE_LD || dep_insn_type == TYPE_LDSYM)
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cost += alpha_memory_latency-1;
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if (alpha_cpu == PROCESSOR_EV5)
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{
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/* And the lord DEC saith: "A special bypass provides an effective
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@ -245,10 +245,11 @@ extern enum alpha_fp_trap_mode alpha_fptm;
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extern char *m88k_short_data;
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#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
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extern char *alpha_cpu_string; /* For -mcpu=ev[4|5] */
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extern char *alpha_cpu_string; /* For -mcpu= */
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extern char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
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extern char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
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extern char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
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extern char *alpha_mlat_string; /* For -mmemory-latency= */
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#define TARGET_OPTIONS \
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{ \
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@ -256,6 +257,7 @@ extern char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
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{"fp-rounding-mode=", &alpha_fprm_string}, \
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{"fp-trap-mode=", &alpha_fptm_string}, \
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{"trap-precision=", &alpha_tp_string}, \
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{"memory-latency=", &alpha_mlat_string}, \
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}
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/* Sometimes certain combinations of command options do not make sense
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@ -792,15 +794,17 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
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reduce the impact of not being able to allocate a pseudo to a
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hard register. */
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#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
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(((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) ? 2 : 20)
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#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
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(TARGET_CIX || ((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
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? 2 : 4+2*alpha_memory_latency)
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/* A C expressions returning the cost of moving data of MODE from a register to
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or from memory.
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On the Alpha, bump this up a bit. */
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#define MEMORY_MOVE_COST(MODE) 6
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extern int alpha_memory_latency;
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#define MEMORY_MOVE_COST(MODE) (2*alpha_memory_latency)
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/* Provide the cost of a branch. Exact meaning under development. */
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#define BRANCH_COST 5
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@ -1107,6 +1111,10 @@ extern int alpha_compare_fp_p;
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IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
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extern void alpha_need_linkage ();
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/* This macro defines the start of an assembly comment. */
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#define ASM_COMMENT_START " #"
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/* This macro produces the initial definition of a function name. On the
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Alpha, we need to save the function name for the prologue and epilogue. */
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@ -45,11 +45,13 @@
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;; the address, BBOX, used for branches, EBOX, used for integer
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;; operations, and FBOX, used for FP operations.
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;; Memory delivers its result in three cycles.
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;; Memory delivers its result in three cycles. Actually return one and
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;; take care of this in adjust_cost, since we want to handle user-defined
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;; memory latencies.
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(define_function_unit "ev4_abox" 1 0
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(and (eq_attr "cpu" "ev4")
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(eq_attr "type" "ld,ldsym,st"))
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3 1)
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1 1)
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;; Branches have no delay cost, but do tie up the unit for two cycles.
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(define_function_unit "ev4_bbox" 1 1
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@ -127,10 +129,11 @@
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1 1)
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;; Memory takes at least 2 clocks, and load cannot dual issue with stores.
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;; Return one from here and fix up with user-defined latencies in adjust_cost.
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(define_function_unit "ev5_ebox" 2 0
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(and (eq_attr "cpu" "ev5")
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(eq_attr "type" "ld,ldsym"))
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2 1)
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1 1)
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(define_function_unit "ev5_e0" 1 0
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(and (eq_attr "cpu" "ev5")
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