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Add initial qualcomm support.

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gcc/
	* config/aarch64/aarch64-cores.def (qdf24xx): New.
	* config/aarch64/aarch64-tune.md: Regenerated.
	* config/arm/arm-cores.def (qdf24xx): New.
	* config/arm/arm-tables.opt, config/arm/arm-tune.md: Regenerated.
	* config/arm/bpabi.h (BE8_LINK_SPEC): Add qdf24xx support.
	* doc/invoke.texi (AArch64 Options/-mtune): Add "qdf24xx".
	(ARM Options/-mtune); Likewise.

From-SVN: r230268
This commit is contained in:
Jim Wilson 2015-11-12 17:27:13 +00:00 committed by Jim Wilson
parent fbfae2f089
commit bc77eb4b51
8 changed files with 22 additions and 4 deletions
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10
gcc/ChangeLog
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@ -1,3 +1,13 @@
2015-11-12 Jim Wilson <jim.wilson@linaro.org>
* config/aarch64/aarch64-cores.def (qdf24xx): New.
* config/aarch64/aarch64-tune.md: Regenerated.
* config/arm/arm-cores.def (qdf24xx): New.
* config/arm/arm-tables.opt, config/arm/arm-tune.md: Regenerated.
* config/arm/bpabi.h (BE8_LINK_SPEC): Add qdf24xx support.
* doc/invoke.texi (AArch64 Options/-mtune): Add "qdf24xx".
(ARM Options/-mtune); Likewise.
2015-11-12 Martin Liska <mliska@suse.cz>
* config/i386/i386.c (ix86_valid_target_attribute_p):

1
gcc/config/aarch64/aarch64-cores.def
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@ -44,6 +44,7 @@ AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AA
AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07")
AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08")
AARCH64_CORE("exynos-m1", exynosm1, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa72, "0x53", "0x001")
AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57, "0x51", "0x800")
AARCH64_CORE("thunderx", thunderx, thunderx, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx, "0x43", "0x0a1")
AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, "0x50", "0x000")

2
gcc/config/aarch64/aarch64-tune.md
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@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune"
"cortexa53,cortexa57,cortexa72,exynosm1,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
"cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))

1
gcc/config/arm/arm-cores.def
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@ -169,6 +169,7 @@ ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED
ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("exynos-m1", exynosm1, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1)
/* V8 big.LITTLE implementations */

3
gcc/config/arm/arm-tables.opt
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@ -315,6 +315,9 @@ Enum(processor_type) String(cortex-a72) Value(cortexa72)
EnumValue
Enum(processor_type) String(exynos-m1) Value(exynosm1)
EnumValue
Enum(processor_type) String(qdf24xx) Value(qdf24xx)
EnumValue
Enum(processor_type) String(xgene1) Value(xgene1)

4
gcc/config/arm/arm-tune.md
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@ -33,6 +33,6 @@
cortexm7,cortexm4,cortexm3,
marvell_pj4,cortexa15cortexa7,cortexa17cortexa7,
cortexa53,cortexa57,cortexa72,
exynosm1,xgene1,cortexa57cortexa53,
cortexa72cortexa53"
exynosm1,qdf24xx,xgene1,
cortexa57cortexa53,cortexa72cortexa53"
(const (symbol_ref "((enum attr_tune) arm_tune)")))

2
gcc/config/arm/bpabi.h
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@ -74,6 +74,7 @@
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
|mcpu=exynos-m1 \
|mcpu=qdf24xx \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \
@ -99,6 +100,7 @@
|mcpu=cortex-a72 \
|mcpu=cortex-a72.cortex-a53 \
|mcpu=exynos-m1 \
|mcpu=qdf24xx \
|mcpu=xgene1 \
|mcpu=cortex-m1.small-multiply \
|mcpu=cortex-m0.small-multiply \

3
gcc/doc/invoke.texi
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@ -12577,7 +12577,7 @@ processors implementing the target architecture.
Specify the name of the target processor for which GCC should tune the
performance of the code. Permissible values for this option are:
@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
@samp{exynos-m1}, @samp{thunderx}, @samp{xgene1}.
@samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx}, @samp{xgene1}.
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible values for this
@ -13564,6 +13564,7 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{cortex-m0.small-multiply},
@samp{cortex-m0plus.small-multiply},
@samp{exynos-m1},
@samp{qdf24xx},
@samp{marvell-pj4},
@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
@samp{fa526}, @samp{fa626},