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AVR: Add an RTL peephole to tweak lower_reg:QI o= cst.

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For operations like  X o= CST, regalloc may spill l-reg X to a d-reg:
   D =  X
   D o= CST
   X =  D
where it is better to instead
   D =  CST
   X o= D
This patch adds an according RTL peephole.

gcc/
	* config/avr/avr.md: Add a peephole2 that improves bit operations
	with a lower register and a constant.
This commit is contained in:
Georg-Johann Lay 2024-11-06 09:46:40 +01:00
parent e30bc91e96
commit bbfba1cc92
1 changed files with 31 additions and 0 deletions
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31
gcc/config/avr/avr.md
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@ -4745,6 +4745,37 @@
(clobber (reg:CC REG_CC))])])
;; For operations like X o= CST, regalloc may spill l-reg X to a d-reg:
;; D = X
;; D o= CST
;; X = D
;; where it is better to instead
;; D = CST
;; X o= D
(define_peephole2
[; Move l-reg to d-reg for the purpose of BITOP.
(parallel [(set (match_operand:ALL1 0 "d_register_operand")
(match_operand:ALL1 1 "l_register_operand"))
(clobber (reg:CC REG_CC))])
(parallel [(set (match_dup 0)
(bitop:ALL1 (match_dup 0)
(match_operand:ALL1 2 "const_operand")))
(clobber (reg:CC REG_CC))])
; Move d-reg result back to l-reg.
(parallel [(set (match_dup 1)
(match_dup 0))
(clobber (reg:CC REG_CC))])]
"peep2_reg_dead_p (3, operands[0])"
[; "movqi_insn"
(parallel [(set (match_dup 0)
(match_dup 2))
(clobber (reg:CC REG_CC))])
(parallel [(set (match_dup 1)
(bitop:ALL1 (match_dup 1)
(match_dup 0)))
(clobber (reg:CC REG_CC))])])
;; swap swap swap swap swap swap swap swap swap swap swap swap swap swap swap
;; swap