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ldmstm.md (ldm2_ia, [...]): Add condition !arm_arch7 to these insns.
* config/arm/ldmstm.md (ldm2_ia, stm2_ia, ldm2_ib, stm2_ib, ldm2_da, stm2_da, ldm2_db, stm2_db): Add condition !arm_arch7 to these insns. (ldrd, ldrd_reg1, ldrd_reg2 and peephole2): New insn patterns and related peephole2. (strd, strd_reg1, strd_reg2 and peephole2): New insn patterns and related peephole2. * config/arm/arm-protos.h (arm_check_ldrd_operands): New prototype. (arm_legitimate_ldrd_p): New prototype. (arm_output_ldrd): New prototype. * config/arm/arm.c (arm_check_ldrd_operands): New function. (arm_legitimate_ldrd_p): New function. (arm_output_ldrd): New function. * gcc.target/arm/pr45335.c: New test. * gcc.target/arm/pr45335-2.c: New test. * gcc.target/arm/pr45335-3.c: New test. * gcc.target/arm/pr40457-1.c: Add another possible output "ldrd". * gcc.target/arm/pr40457-2.c: Changed to store 3 words. * gcc.target/arm/pr40457-3.c: Changed to store 3 words. From-SVN: r174940
This commit is contained in:
Wei Guozhi
Wei Guozhi
parent
d351f68e1c
commit
ba68a139ac
@ -1,3 +1,19 @@
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2011-06-10 Wei Guozhi <carrot@google.com>
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PR target/45335
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* config/arm/ldmstm.md (ldm2_ia, stm2_ia, ldm2_ib, stm2_ib, ldm2_da,
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stm2_da, ldm2_db, stm2_db): Add condition !arm_arch7 to these insns.
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(ldrd, ldrd_reg1, ldrd_reg2 and peephole2): New insn patterns and
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related peephole2.
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(strd, strd_reg1, strd_reg2 and peephole2): New insn patterns and
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related peephole2.
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* config/arm/arm-protos.h (arm_check_ldrd_operands): New prototype.
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(arm_legitimate_ldrd_p): New prototype.
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(arm_output_ldrd): New prototype.
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* config/arm/arm.c (arm_check_ldrd_operands): New function.
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(arm_legitimate_ldrd_p): New function.
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(arm_output_ldrd): New function.
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2011-06-10 David Li <davidxl@google.com>
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* cgraphunit.c (cgraph_finalize_compilation_unit): Pass dump.
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@ -153,6 +153,9 @@ extern const char *arm_output_memory_barrier (rtx *);
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extern const char *arm_output_sync_insn (rtx, rtx *);
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extern unsigned int arm_sync_loop_insns (rtx , rtx *);
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extern int arm_attr_length_push_multi(rtx, rtx);
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extern bool arm_check_ldrd_operands (rtx, rtx, rtx, rtx);
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extern bool arm_legitimate_ldrd_p (rtx, rtx, rtx, rtx, bool);
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extern int arm_output_ldrd (rtx, rtx, rtx, rtx, rtx, bool);
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#if defined TREE_CODE
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extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
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@ -23853,4 +23853,234 @@ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
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return 4;
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}
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/* Check the validity of operands in an ldrd/strd instruction. */
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bool
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arm_check_ldrd_operands (rtx reg1, rtx reg2, rtx off1, rtx off2)
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{
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HOST_WIDE_INT offset1 = 0;
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HOST_WIDE_INT offset2 = 0;
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int regno1 = REGNO (reg1);
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int regno2 = REGNO (reg2);
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HOST_WIDE_INT max_offset = 1020;
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if (TARGET_ARM)
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max_offset = 255;
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if (off1 != NULL_RTX)
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offset1 = INTVAL (off1);
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if (off2 != NULL_RTX)
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offset2 = INTVAL (off2);
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/* The offset range of LDRD is [-max_offset, max_offset]. Here we check if
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both offsets lie in the range [-max_offset, max_offset+4]. If one of the
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offsets is max_offset+4, the following condition
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((offset1 + 4) == offset2)
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will ensure offset1 to be max_offset, suitable for instruction LDRD. */
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if ((offset1 > (max_offset + 4)) || (offset1 < -max_offset)
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|| ((offset1 & 3) != 0))
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return false;
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if ((offset2 > (max_offset + 4)) || (offset2 < -max_offset)
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|| ((offset2 & 3) != 0))
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return false;
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if ((offset1 + 4) == offset2)
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{
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if (TARGET_THUMB2)
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return true;
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/* TARGET_ARM */
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if (((regno1 & 1) == 0) && ((regno1 + 1) == regno2)) /* ldrd */
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return true;
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if ((regno1 < regno2) && ((offset1 <= 4) && (offset1 >= -8))) /* ldm */
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return true;
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}
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if ((offset2 + 4) == offset1)
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{
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if (TARGET_THUMB2)
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return true;
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/* TARGET_ARM */
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if (((regno2 & 1) == 0) && ((regno2 + 1) == regno1)) /* ldrd */
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return true;
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if ((regno2 < regno1) && ((offset2 <= 4) && (offset2 >= -8))) /* ldm */
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return true;
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}
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return false;
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}
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/* Check if the two memory accesses can be merged to an ldrd/strd instruction.
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That is they use the same base register, and the gap between constant
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offsets should be 4. */
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bool
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arm_legitimate_ldrd_p (rtx reg1, rtx reg2, rtx mem1, rtx mem2, bool ldrd)
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{
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rtx base1, base2;
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rtx offset1 = NULL_RTX;
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rtx offset2 = NULL_RTX;
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rtx addr1 = XEXP (mem1, 0);
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rtx addr2 = XEXP (mem2, 0);
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if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
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return false;
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if (REG_P (addr1))
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base1 = addr1;
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else if (GET_CODE (addr1) == PLUS)
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{
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base1 = XEXP (addr1, 0);
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offset1 = XEXP (addr1, 1);
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if (!REG_P (base1) || (GET_CODE (offset1) != CONST_INT))
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return false;
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}
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else
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return false;
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if (REG_P (addr2))
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base2 = addr2;
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else if (GET_CODE (addr2) == PLUS)
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{
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base2 = XEXP (addr2, 0);
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offset2 = XEXP (addr2, 1);
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if (!REG_P (base2) || (GET_CODE (offset2) != CONST_INT))
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return false;
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}
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else
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return false;
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if (base1 != base2)
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return false;
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if (ldrd && ((reg1 == reg2) || (reg1 == base1)))
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return false;
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return arm_check_ldrd_operands (reg1, reg2, offset1, offset2);
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}
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/* Output instructions for ldrd and count the number of bytes has been
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outputted. Do not actually output instructions if EMIT_P is false. */
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int
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arm_output_ldrd (rtx reg1, rtx reg2, rtx base, rtx off1, rtx off2, bool emit_p)
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{
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int length = 0;
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rtx operands[5];
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HOST_WIDE_INT offset1 = 0;
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HOST_WIDE_INT offset2 = 0;
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if (off1 != NULL_RTX)
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offset1 = INTVAL (off1);
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else
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off1 = GEN_INT (0);
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if (off2 != NULL_RTX)
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offset2 = INTVAL (off2);
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else
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off2 = GEN_INT (0);
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if (offset1 > offset2)
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{
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rtx tmp;
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HOST_WIDE_INT t = offset1; offset1 = offset2; offset2 = t;
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tmp = off1; off1 = off2; off2 = tmp;
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tmp = reg1; reg1 = reg2; reg2 = tmp;
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}
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operands[0] = reg1;
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operands[1] = reg2;
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operands[2] = base;
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operands[3] = off1;
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operands[4] = off2;
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if (TARGET_THUMB2)
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{
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if (fix_cm3_ldrd && (base == reg1))
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{
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if (offset1 <= -256)
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{
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if (emit_p)
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output_asm_insn ("sub\t%2, %2, %n3", operands);
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length = 4;
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if (emit_p)
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output_asm_insn ("ldr\t%1, [%2, #4]", operands);
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if (low_register_operand (reg2, SImode)
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&& low_register_operand (base, SImode))
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length += 2;
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else
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length += 4;
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if (emit_p)
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output_asm_insn ("ldr\t%0, [%2]", operands);
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if (low_register_operand (base, SImode))
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length += 2;
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else
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length += 4;
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}
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else
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{
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if (emit_p)
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output_asm_insn ("ldr\t%1, [%2, %4]", operands);
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if (low_register_operand (reg2, SImode) && (offset2 >= 0)
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&& low_register_operand (base, SImode) && (offset2 < 128))
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length += 2;
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else
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length += 4;
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if (emit_p)
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output_asm_insn ("ldr\t%0, [%2, %3]", operands);
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if (low_register_operand (base, SImode)
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&& (offset1 >= 0) && (offset1 < 128))
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length += 2;
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else
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length += 4;
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}
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}
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else
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{
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if (emit_p)
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output_asm_insn ("ldrd\t%0, %1, [%2, %3]", operands);
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length = 4;
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}
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}
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else /* TARGET_ARM */
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{
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if ((REGNO (reg2) == (REGNO (reg1) + 1)) && ((REGNO (reg1) & 1) == 0))
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{
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if (emit_p)
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output_asm_insn ("ldrd\t%0, %1, [%2, %3]", operands);
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length = 4;
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}
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else
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{
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if (emit_p)
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{
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switch (offset1)
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{
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case -8:
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output_asm_insn ("ldm%(db%)\t%2, {%0, %1}", operands);
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break;
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case -4:
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output_asm_insn ("ldm%(da%)\t%2, {%0, %1}", operands);
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break;
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case 0:
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output_asm_insn ("ldm%(ia%)\t%2, {%0, %1}", operands);
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break;
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case 4:
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output_asm_insn ("ldm%(ib%)\t%2, {%0, %1}", operands);
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break;
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default:
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gcc_unreachable ();
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}
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}
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length = 4;
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}
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}
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return length;
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}
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#include "gt-arm.h"
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@ -852,7 +852,7 @@
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(set (match_operand:SI 2 "arm_hard_register_operand" "")
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(mem:SI (plus:SI (match_dup 3)
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(const_int 4))))])]
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"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
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"TARGET_32BIT && !arm_arch7 && XVECLEN (operands[0], 0) == 2"
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"ldm%(ia%)\t%3, {%1, %2}"
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[(set_attr "type" "load2")
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(set_attr "predicable" "yes")])
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@ -901,7 +901,7 @@
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(match_operand:SI 1 "arm_hard_register_operand" ""))
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(set (mem:SI (plus:SI (match_dup 3) (const_int 4)))
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(match_operand:SI 2 "arm_hard_register_operand" ""))])]
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"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
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"TARGET_32BIT && !arm_arch7 && XVECLEN (operands[0], 0) == 2"
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"stm%(ia%)\t%3, {%1, %2}"
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[(set_attr "type" "store2")
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(set_attr "predicable" "yes")])
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@ -939,7 +939,7 @@
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(set (match_operand:SI 2 "arm_hard_register_operand" "")
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(mem:SI (plus:SI (match_dup 3)
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(const_int 8))))])]
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"TARGET_ARM && XVECLEN (operands[0], 0) == 2"
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"TARGET_ARM && !arm_arch7 && XVECLEN (operands[0], 0) == 2"
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"ldm%(ib%)\t%3, {%1, %2}"
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[(set_attr "type" "load2")
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(set_attr "predicable" "yes")])
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@ -965,7 +965,7 @@
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(match_operand:SI 1 "arm_hard_register_operand" ""))
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(set (mem:SI (plus:SI (match_dup 3) (const_int 8)))
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(match_operand:SI 2 "arm_hard_register_operand" ""))])]
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"TARGET_ARM && XVECLEN (operands[0], 0) == 2"
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"TARGET_ARM && !arm_arch7 && XVECLEN (operands[0], 0) == 2"
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"stm%(ib%)\t%3, {%1, %2}"
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[(set_attr "type" "store2")
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(set_attr "predicable" "yes")])
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@ -990,7 +990,7 @@
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(const_int -4))))
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(set (match_operand:SI 2 "arm_hard_register_operand" "")
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(mem:SI (match_dup 3)))])]
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"TARGET_ARM && XVECLEN (operands[0], 0) == 2"
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"TARGET_ARM && !arm_arch7 && XVECLEN (operands[0], 0) == 2"
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"ldm%(da%)\t%3, {%1, %2}"
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[(set_attr "type" "load2")
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(set_attr "predicable" "yes")])
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@ -1015,7 +1015,7 @@
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(match_operand:SI 1 "arm_hard_register_operand" ""))
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(set (mem:SI (match_dup 3))
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(match_operand:SI 2 "arm_hard_register_operand" ""))])]
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"TARGET_ARM && XVECLEN (operands[0], 0) == 2"
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"TARGET_ARM && !arm_arch7 && XVECLEN (operands[0], 0) == 2"
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"stm%(da%)\t%3, {%1, %2}"
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[(set_attr "type" "store2")
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(set_attr "predicable" "yes")])
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@ -1041,7 +1041,7 @@
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(set (match_operand:SI 2 "arm_hard_register_operand" "")
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(mem:SI (plus:SI (match_dup 3)
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(const_int -4))))])]
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"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
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"TARGET_32BIT && !arm_arch7 && XVECLEN (operands[0], 0) == 2"
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"ldm%(db%)\t%3, {%1, %2}"
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[(set_attr "type" "load2")
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(set_attr "predicable" "yes")])
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@ -1067,7 +1067,7 @@
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(match_operand:SI 1 "arm_hard_register_operand" ""))
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(set (mem:SI (plus:SI (match_dup 3) (const_int -4)))
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(match_operand:SI 2 "arm_hard_register_operand" ""))])]
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"TARGET_32BIT && XVECLEN (operands[0], 0) == 2"
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"TARGET_32BIT && !arm_arch7 && XVECLEN (operands[0], 0) == 2"
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"stm%(db%)\t%3, {%1, %2}"
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[(set_attr "type" "store2")
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(set_attr "predicable" "yes")])
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@ -1189,3 +1189,207 @@
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FAIL;
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})
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(define_insn "*ldrd"
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[(set (match_operand:SI 0 "arm_hard_register_operand" "")
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(mem:SI (plus:SI (match_operand:SI 2 "s_register_operand" "rk")
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(match_operand:SI 3 "const_int_operand" ""))))
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(set (match_operand:SI 1 "arm_hard_register_operand" "")
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(mem:SI (plus:SI (match_dup 2)
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(match_operand:SI 4 "const_int_operand" ""))))]
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"TARGET_32BIT && arm_arch7
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&& arm_check_ldrd_operands (operands[0], operands[1],
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operands[3], operands[4])"
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"*
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arm_output_ldrd (operands[0], operands[1],
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operands[2], operands[3], operands[4], true);
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return \"\";
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"
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[(set (attr "length")
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(symbol_ref ("arm_output_ldrd (operands[0], operands[1], operands[2],
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operands[3], operands[4], false)")))]
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)
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(define_insn "*ldrd_reg1"
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[(set (match_operand:SI 0 "arm_hard_register_operand" "")
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(mem:SI (match_operand:SI 2 "s_register_operand" "rk")))
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(set (match_operand:SI 1 "arm_hard_register_operand" "")
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(mem:SI (plus:SI (match_dup 2)
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(match_operand:SI 3 "const_int_operand" ""))))]
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"TARGET_32BIT && arm_arch7
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&& arm_check_ldrd_operands (operands[0], operands[1], NULL_RTX, operands[3])"
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"*
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arm_output_ldrd (operands[0], operands[1],
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operands[2], NULL_RTX, operands[3], true);
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return \"\";
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"
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[(set (attr "length")
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(symbol_ref ("arm_output_ldrd (operands[0], operands[1], operands[2],
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NULL_RTX, operands[3], false)")))]
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)
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(define_insn "*ldrd_reg2"
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[(set (match_operand:SI 0 "arm_hard_register_operand" "")
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(mem:SI (plus:SI (match_operand:SI 2 "s_register_operand" "rk")
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(match_operand:SI 3 "const_int_operand" ""))))
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(set (match_operand:SI 1 "arm_hard_register_operand" "")
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(mem:SI (match_dup 2)))]
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"TARGET_32BIT && arm_arch7
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&& arm_check_ldrd_operands (operands[0], operands[1], operands[3], NULL_RTX)"
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"*
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arm_output_ldrd (operands[0], operands[1],
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operands[2], operands[3], NULL_RTX, true);
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||||
return \"\";
|
||||
"
|
||||
[(set (attr "length")
|
||||
(symbol_ref ("arm_output_ldrd (operands[0], operands[1], operands[2],
|
||||
operands[3], NULL_RTX, false)")))]
|
||||
)
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:SI 0 "arm_general_register_operand" "")
|
||||
(match_operand:SI 2 "memory_operand" ""))
|
||||
(set (match_operand:SI 1 "arm_general_register_operand" "")
|
||||
(match_operand:SI 3 "memory_operand" ""))]
|
||||
"TARGET_32BIT && arm_arch7
|
||||
&& arm_legitimate_ldrd_p (operands[0], operands[1],
|
||||
operands[2], operands[3], true)"
|
||||
[(parallel [(set (match_operand:SI 0 "arm_general_register_operand" "")
|
||||
(match_operand:SI 2 "memory_operand" ""))
|
||||
(set (match_operand:SI 1 "arm_general_register_operand" "")
|
||||
(match_operand:SI 3 "memory_operand" ""))])]
|
||||
""
|
||||
)
|
||||
|
||||
(define_insn "*strd"
|
||||
[(set (mem:SI (plus:SI (match_operand:SI 2 "s_register_operand" "rk")
|
||||
(match_operand:SI 3 "const_int_operand" "")))
|
||||
(match_operand:SI 0 "arm_hard_register_operand" ""))
|
||||
(set (mem:SI (plus:SI (match_dup 2)
|
||||
(match_operand:SI 4 "const_int_operand" "")))
|
||||
(match_operand:SI 1 "arm_hard_register_operand" ""))]
|
||||
"TARGET_32BIT && arm_arch7
|
||||
&& arm_check_ldrd_operands (operands[0], operands[1],
|
||||
operands[3], operands[4])"
|
||||
"*
|
||||
{
|
||||
HOST_WIDE_INT offset1 = INTVAL (operands[3]);
|
||||
HOST_WIDE_INT offset2 = INTVAL (operands[4]);
|
||||
if (offset1 > offset2)
|
||||
{
|
||||
rtx tmp = operands[0]; operands[0] = operands[1]; operands[1] = tmp;
|
||||
tmp = operands[3]; operands[3] = operands[4]; operands[4] = tmp;
|
||||
offset1 = INTVAL (operands[3]);
|
||||
offset2 = INTVAL (operands[4]);
|
||||
}
|
||||
if (TARGET_THUMB2)
|
||||
return \"strd\\t%0, %1, [%2, %3]\";
|
||||
else /* TARGET_ARM */
|
||||
{
|
||||
if ((REGNO (operands[1]) == (REGNO (operands[0]) + 1))
|
||||
&& ((REGNO (operands[0]) & 1) == 0))
|
||||
return \"strd\\t%0, %1, [%2, %3]\";
|
||||
else if (offset1 == -8)
|
||||
return \"stm%(db%)\\t%2, {%0, %1}\";
|
||||
else /* offset1 == 4 */
|
||||
return \"stm%(ib%)\\t%2, {%0, %1}\";
|
||||
}
|
||||
}"
|
||||
[(set_attr "length" "4")]
|
||||
)
|
||||
|
||||
(define_insn "*strd_reg1"
|
||||
[(set (mem:SI (match_operand:SI 2 "s_register_operand" "rk"))
|
||||
(match_operand:SI 0 "arm_hard_register_operand" ""))
|
||||
(set (mem:SI (plus:SI (match_dup 2)
|
||||
(match_operand:SI 3 "const_int_operand" "")))
|
||||
(match_operand:SI 1 "arm_hard_register_operand" ""))]
|
||||
"TARGET_32BIT && arm_arch7
|
||||
&& arm_check_ldrd_operands (operands[0], operands[1], NULL_RTX, operands[3])"
|
||||
"*
|
||||
{
|
||||
HOST_WIDE_INT offset2 = INTVAL (operands[3]);
|
||||
if (TARGET_THUMB2)
|
||||
{
|
||||
if (offset2 == 4)
|
||||
return \"strd\\t%0, %1, [%2]\";
|
||||
else
|
||||
return \"strd\\t%1, %0, [%2, %3]\";
|
||||
}
|
||||
else /* TARGET_ARM */
|
||||
{
|
||||
if (offset2 == 4)
|
||||
{
|
||||
if ((REGNO (operands[1]) == (REGNO (operands[0]) + 1))
|
||||
&& ((REGNO (operands[0]) & 1) == 0))
|
||||
return \"strd\\t%0, %1, [%2]\";
|
||||
else
|
||||
return \"stm%(ia%)\\t%2, {%0, %1}\";
|
||||
}
|
||||
else /* offset2 == -4 */
|
||||
{
|
||||
if ((REGNO (operands[0]) == (REGNO (operands[1]) + 1))
|
||||
&& ((REGNO (operands[1]) & 1) == 0))
|
||||
return \"strd\\t%1, %0, [%2, %3]\";
|
||||
else
|
||||
return \"stm%(da%)\\t%2, {%1, %0}\";
|
||||
}
|
||||
}
|
||||
}"
|
||||
[(set_attr "length" "4")]
|
||||
)
|
||||
|
||||
(define_insn "*strd_reg2"
|
||||
[(set (mem:SI (plus:SI (match_operand:SI 2 "s_register_operand" "rk")
|
||||
(match_operand:SI 3 "const_int_operand" "")))
|
||||
(match_operand:SI 0 "arm_hard_register_operand" ""))
|
||||
(set (mem:SI (match_dup 2))
|
||||
(match_operand:SI 1 "arm_hard_register_operand" ""))]
|
||||
"TARGET_32BIT && arm_arch7
|
||||
&& arm_check_ldrd_operands (operands[0], operands[1], operands[3], NULL_RTX)"
|
||||
"*
|
||||
{
|
||||
HOST_WIDE_INT offset1 = INTVAL (operands[3]);
|
||||
if (TARGET_THUMB2)
|
||||
{
|
||||
if (offset1 == -4)
|
||||
return \"strd\\t%0, %1, [%2, %3]\";
|
||||
else
|
||||
return \"strd\\t%1, %0, [%2]\";
|
||||
}
|
||||
else /* TARGET_ARM */
|
||||
{
|
||||
if (offset1 == -4)
|
||||
{
|
||||
if ((REGNO (operands[1]) == (REGNO (operands[0]) + 1))
|
||||
&& ((REGNO (operands[0]) & 1) == 0))
|
||||
return \"strd\\t%0, %1, [%2, %3]\";
|
||||
else
|
||||
return \"stm%(da%)\\t%2, {%0, %1}\";
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((REGNO (operands[0]) == (REGNO (operands[1]) + 1))
|
||||
&& ((REGNO (operands[1]) & 1) == 0))
|
||||
return \"strd\\t%1, %0, [%2]\";
|
||||
else
|
||||
return \"stm%(ia%)\\t%2, {%1, %0}\";
|
||||
}
|
||||
}
|
||||
}"
|
||||
[(set_attr "length" "4")]
|
||||
)
|
||||
|
||||
(define_peephole2
|
||||
[(set (match_operand:SI 2 "memory_operand" "")
|
||||
(match_operand:SI 0 "arm_general_register_operand" ""))
|
||||
(set (match_operand:SI 3 "memory_operand" "")
|
||||
(match_operand:SI 1 "arm_general_register_operand" ""))]
|
||||
"TARGET_32BIT && arm_arch7
|
||||
&& arm_legitimate_ldrd_p (operands[0], operands[1],
|
||||
operands[2], operands[3], false)"
|
||||
[(parallel [(set (match_operand:SI 2 "memory_operand" "")
|
||||
(match_operand:SI 0 "arm_general_register_operand" ""))
|
||||
(set (match_operand:SI 3 "memory_operand" "")
|
||||
(match_operand:SI 1 "arm_general_register_operand" ""))])]
|
||||
""
|
||||
)
|
||||
|
||||
@ -1,3 +1,13 @@
|
||||
2011-06-10 Wei Guozhi <carrot@google.com>
|
||||
|
||||
PR target/45335
|
||||
* gcc.target/arm/pr45335.c: New test.
|
||||
* gcc.target/arm/pr45335-2.c: New test.
|
||||
* gcc.target/arm/pr45335-3.c: New test.
|
||||
* gcc.target/arm/pr40457-1.c: Add another possible output "ldrd".
|
||||
* gcc.target/arm/pr40457-2.c: Changed to store 3 words.
|
||||
* gcc.target/arm/pr40457-3.c: Changed to store 3 words.
|
||||
|
||||
2011-06-10 Paolo Carlini <paolo.carlini@oracle.com>
|
||||
|
||||
PR c++/41769
|
||||
|
||||
@ -7,4 +7,4 @@ int bar(int* p)
|
||||
return x;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "ldm" } } */
|
||||
/* { dg-final { scan-assembler "ldm|ldrd" } } */
|
||||
|
||||
@ -5,6 +5,7 @@ void foo(int* p)
|
||||
{
|
||||
p[0] = 1;
|
||||
p[1] = 0;
|
||||
p[2] = 2;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "stm" } } */
|
||||
|
||||
@ -5,6 +5,7 @@ void foo(int* p)
|
||||
{
|
||||
p[0] = 1;
|
||||
p[1] = 0;
|
||||
p[2] = 2;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "stm" } } */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user