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({zero_,}extend[qh]i[dsh]i2): Rework TARGET_BYTE_OPS cases.
(mov[hq]i): Likewise.
(extend[qh]i[hsd]i2x): Add missing cases and fix typo in constraint.
(reload_{in,out}[qh]i): Disable for TARGET_BYTE_OPS.
From-SVN: r14496
This commit is contained in:
Richard Kenner
parent
e008606e02
commit
b9a2d59104
@ -811,13 +811,19 @@
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ldbu %0,%1"
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[(set_attr "type" "shift,ld")])
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(define_insn "zero_extendqisi2"
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
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""
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"! TARGET_BYTE_OPS"
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"zapnot %1,1,%0"
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[(set_attr "type" "shift")])
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(define_expand "zero_extendqisi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
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""
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"")
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
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@ -827,13 +833,19 @@
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ldbu %0,%1"
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[(set_attr "type" "shift,ld")])
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(define_insn "zero_extendqidi2"
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
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""
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"! TARGET_BYTE_OPS"
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"zapnot %1,1,%0"
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[(set_attr "type" "shift")])
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(define_expand "zero_extendqidi2"
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[(set (match_operand:DI 0 "register_operand" "")
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(zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
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""
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"")
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
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@ -843,13 +855,19 @@
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ldwu %0,%1"
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[(set_attr "type" "shift,ld")])
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(define_insn "zero_extendhisi2"
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
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""
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"! TARGET_BYTE_OPS"
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"zapnot %1,3,%0"
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[(set_attr "type" "shift")])
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(define_expand "zero_extendhisi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
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""
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"")
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
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@ -859,13 +877,19 @@
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ldwu %0,%1"
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[(set_attr "type" "shift,ld")])
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(define_insn "zero_extendhidi2"
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
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""
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"zapnot %1,3,%0"
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[(set_attr "type" "shift")])
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(define_expand "zero_extendhidi2"
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[(set (match_operand:DI 0 "register_operand" "")
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(zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
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""
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"")
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(define_insn "zero_extendsidi2"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
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@ -983,7 +1007,7 @@
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(define_expand "extendqihi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:QI 1 "reg_or_unaligned_mem_operand" "")
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(ashift:DI (match_operand:QI 1 "some_operand" "")
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(const_int 56)))
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(set (match_operand:HI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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@ -991,9 +1015,16 @@
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""
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"
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{
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/* If we have a MEM (must be unaligned), extend to DImode (which we do
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if (TARGET_BYTE_OPS)
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{
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emit_insn (gen_extendqihi2x (operands[0],
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force_reg (QImode, operands[1])));
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DONE;
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}
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/* If we have an unaligned MEM, extend to DImode (which we do
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specially) and then copy to the result. */
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if (GET_CODE (operands[1]) == MEM)
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if (unaligned_memory_operand (operands[1], HImode))
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{
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rtx temp = gen_reg_rtx (DImode);
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@ -1003,27 +1034,48 @@
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}
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operands[0] = gen_lowpart (DImode, operands[0]);
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operands[1] = gen_lowpart (DImode, operands[1]);
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operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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}")
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(define_insn "extendqidi2x"
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[(set (match_operand:DI 0 "register_operand" "r")
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
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"TARGET_BYTE_OPS"
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"sextb %1,%0"
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[(set_attr "type" "shift")]) ;; not sure what class this belongs to
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[(set_attr "type" "shift")])
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(define_insn "extendhidi2x"
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[(set (match_operand:DI 0 "register_operand" "r")
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[(set (match_operand:DI 0 "register_operand" "=r")
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(sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
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"TARGET_BYTE_OPS"
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"sextw %1,%0"
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[(set_attr "type" "shift")])
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(define_insn "extendqisi2x"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
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"TARGET_BYTE_OPS"
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"sextb %1,%0"
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[(set_attr "type" "shift")])
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(define_insn "extendhisi2x"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
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"TARGET_BYTE_OPS"
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"sextw %1,%0"
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[(set_attr "type" "shift")])
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(define_insn "extendqihi2x"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
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"TARGET_BYTE_OPS"
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"sextb %1,%0"
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[(set_attr "type" "shift")])
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(define_expand "extendqisi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:QI 1 "reg_or_unaligned_mem_operand" "")
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(ashift:DI (match_operand:QI 1 "some_operand" "")
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(const_int 56)))
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(set (match_operand:SI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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@ -1031,9 +1083,16 @@
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""
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"
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{
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/* If we have a MEM (must be unaligned), extend to a DImode form of
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if (TARGET_BYTE_OPS)
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{
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emit_insn (gen_extendqisi2x (operands[0],
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force_reg (QImode, operands[1])));
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DONE;
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}
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/* If we have an unaligned MEM, extend to a DImode form of
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the result (which we do specially). */
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if (GET_CODE (operands[1]) == MEM)
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if (unaligned_memory_operand (operands[1], QImode))
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{
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rtx temp = gen_reg_rtx (DImode);
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@ -1043,13 +1102,13 @@
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}
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operands[0] = gen_lowpart (DImode, operands[0]);
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operands[1] = gen_lowpart (DImode, operands[1]);
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operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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}")
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(define_expand "extendqidi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:QI 1 "reg_or_unaligned_mem_operand" "")
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(ashift:DI (match_operand:QI 1 "some_operand" "")
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(const_int 56)))
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(set (match_operand:DI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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@ -1060,19 +1119,12 @@
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if (TARGET_BYTE_OPS)
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{
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rtx temp = operands[1];
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if (GET_CODE (operands[1]) == MEM)
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{
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temp = gen_reg_rtx (QImode);
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emit_insn (gen_movqi (temp, operands[1]));
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}
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emit_insn (gen_extendqidi2x (operands[0], temp));
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emit_insn (gen_extendqidi2x (operands[0],
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force_reg (QImode, operands[1])));
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DONE;
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}
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if (GET_CODE (operands[1]) == MEM)
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if (unaligned_memory_operand (operands[1], QImode))
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{
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rtx seq
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= gen_unaligned_extendqidi (operands[0],
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@ -1083,13 +1135,13 @@
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DONE;
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}
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operands[1] = gen_lowpart (DImode, operands[1]);
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operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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}")
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(define_expand "extendhisi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:HI 1 "reg_or_unaligned_mem_operand" "")
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(ashift:DI (match_operand:HI 1 "some_operand" "")
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(const_int 48)))
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(set (match_operand:SI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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@ -1097,9 +1149,16 @@
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""
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"
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{
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/* If we have a MEM (must be unaligned), extend to a DImode form of
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if (TARGET_BYTE_OPS)
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{
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emit_insn (gen_extendhisi2x (operands[0],
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force_reg (HImode, operands[1])));
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DONE;
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}
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/* If we have an unaligned MEM, extend to a DImode form of
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the result (which we do specially). */
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if (GET_CODE (operands[1]) == MEM)
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if (unaligned_memory_operand (operands[1], HImode))
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{
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rtx temp = gen_reg_rtx (DImode);
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@ -1109,13 +1168,13 @@
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}
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operands[0] = gen_lowpart (DImode, operands[0]);
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operands[1] = gen_lowpart (DImode, operands[1]);
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operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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}")
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(define_expand "extendhidi2"
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[(set (match_dup 2)
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(ashift:DI (match_operand:HI 1 "reg_or_unaligned_mem_operand" "")
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(ashift:DI (match_operand:HI 1 "some_operand" "")
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(const_int 48)))
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(set (match_operand:DI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 2)
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@ -1126,19 +1185,12 @@
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if (TARGET_BYTE_OPS)
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{
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rtx temp = operands[1];
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if (GET_CODE (operands[1]) == MEM)
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{
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temp = gen_reg_rtx (HImode);
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emit_insn (gen_movhi (temp, operands[1]));
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}
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emit_insn (gen_extendhidi2x (operands[0], temp));
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emit_insn (gen_extendhidi2x (operands[0],
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force_reg (HImode, operands[1])));
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DONE;
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}
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if (GET_CODE (operands[1]) == MEM)
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if (unaligned_memory_operand (operands[1], HImode))
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{
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rtx seq
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= gen_unaligned_extendhidi (operands[0],
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@ -1149,7 +1201,7 @@
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DONE;
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}
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operands[1] = gen_lowpart (DImode, operands[1]);
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operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
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operands[2] = gen_reg_rtx (DImode);
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}")
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@ -3965,15 +4017,16 @@
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&& ! reg_or_0_operand (operands[1], QImode))
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operands[1] = force_reg (QImode, operands[1]);
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if (! CONSTANT_P (operands[1]) || input_operand (operands[1], QImode))
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;
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else if (GET_CODE (operands[1]) == CONST_INT)
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if (GET_CODE (operands[1]) == CONST_INT
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&& ! input_operand (operands[1], QImode))
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{
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operands[1]
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= alpha_emit_set_const (operands[0], QImode, INTVAL (operands[1]), 3);
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operands[1] = alpha_emit_set_const (operands[0], QImode,
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INTVAL (operands[1]), 3);
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if (rtx_equal_p (operands[0], operands[1]))
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DONE;
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}
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goto def;
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}
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@ -4076,19 +4129,19 @@
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&& ! reg_or_0_operand (operands[1], HImode))
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operands[1] = force_reg (HImode, operands[1]);
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if (! CONSTANT_P (operands[1]) || input_operand (operands[1], HImode))
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;
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else if (GET_CODE (operands[1]) == CONST_INT)
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if (GET_CODE (operands[1]) == CONST_INT
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&& ! input_operand (operands[1], HImode))
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{
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operands[1]
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= alpha_emit_set_const (operands[0], HImode, INTVAL (operands[1]), 3);
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operands[1] = alpha_emit_set_const (operands[0], HImode,
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INTVAL (operands[1]), 3);
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if (rtx_equal_p (operands[0], operands[1]))
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DONE;
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}
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goto def;
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}
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/* If the output is not a register, the input must be. */
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if (GET_CODE (operands[0]) == MEM)
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operands[1] = force_reg (HImode, operands[1]);
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@ -4184,7 +4237,7 @@
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[(parallel [(match_operand:QI 0 "register_operand" "=r")
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(match_operand:QI 1 "unaligned_memory_operand" "m")
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(match_operand:TI 2 "register_operand" "=&r")])]
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""
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"! TARGET_BYTE_OPS"
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"
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{ extern rtx get_unaligned_address ();
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rtx addr = get_unaligned_address (operands[1], 0);
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@ -4206,7 +4259,7 @@
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[(parallel [(match_operand:HI 0 "register_operand" "=r")
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(match_operand:HI 1 "unaligned_memory_operand" "m")
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(match_operand:TI 2 "register_operand" "=&r")])]
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""
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"! TARGET_BYTE_OPS"
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"
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{ extern rtx get_unaligned_address ();
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rtx addr = get_unaligned_address (operands[1], 0);
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@ -4228,7 +4281,7 @@
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[(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
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(match_operand:QI 1 "register_operand" "r")
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(match_operand:TI 2 "register_operand" "=&r")])]
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""
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"! TARGET_BYTE_OPS"
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"
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{ extern rtx get_unaligned_address ();
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@ -4267,7 +4320,7 @@
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[(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
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(match_operand:HI 1 "register_operand" "r")
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(match_operand:TI 2 "register_operand" "=&r")])]
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""
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"! TARGET_BYTE_OPS"
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"
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{ extern rtx get_unaligned_address ();
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