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Finish MIPS4 support, add R5000 support.

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From-SVN: r12732
This commit is contained in:
Ian Lance Taylor 1996-09-17 19:52:34 +00:00
parent 24ba333f7b
commit b8eb88d06f
3 changed files with 749 additions and 472 deletions
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337
gcc/config/mips/mips.c
View File

@ -256,7 +256,8 @@ char mips_reg_names[][8] =
"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
"hi", "lo", "accum","$fcr31","$rap"
"hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
"$fcc5","$fcc6","$fcc7","$rap"
};
/* Mips software names for the registers, used to overwrite the
@ -272,7 +273,8 @@ char mips_sw_reg_names[][8] =
"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
"hi", "lo", "accum","$fcr31","$rap"
"hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
"$fcc5","$fcc6","$fcc7","$rap"
};
/* Map hard register number to register class */
@ -295,7 +297,8 @@ enum reg_class mips_regno_to_class[] =
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
FP_REGS, FP_REGS, FP_REGS, FP_REGS,
HI_REG, LO_REG, HILO_REG, ST_REGS,
GR_REGS
ST_REGS, ST_REGS, ST_REGS, ST_REGS,
ST_REGS, ST_REGS, ST_REGS, GR_REGS
};
/* Map register constraint character to register class. */
@ -524,6 +527,40 @@ mips_const_double_ok (op, mode)
return FALSE;
}
/* Accept the floating point constant 1 in the appropriate mode. */
int
const_float_1_operand (op, mode)
rtx op;
enum machine_mode mode;
{
REAL_VALUE_TYPE d;
static REAL_VALUE_TYPE onedf;
static REAL_VALUE_TYPE onesf;
static int one_initialized;
if (GET_CODE (op) != CONST_DOUBLE
|| mode != GET_MODE (op)
|| (mode != DFmode && mode != SFmode))
return FALSE;
REAL_VALUE_FROM_CONST_DOUBLE (d, op);
/* We only initialize these values if we need them, since we will
never get called unless mips_isa >= 4. */
if (! one_initialized)
{
onedf = REAL_VALUE_ATOF ("1.0", DFmode);
onesf = REAL_VALUE_ATOF ("1.0", SFmode);
one_initialized = TRUE;
}
if (mode == DFmode)
return REAL_VALUES_EQUAL (d, onedf);
else
return REAL_VALUES_EQUAL (d, onesf);
}
/* Return truth value if a memory operand fits in a single instruction
(ie, register + small offset). */
@ -990,6 +1027,10 @@ mips_move_1word (operands, insn, unsignedp)
code1 = GET_CODE (op1);
}
/* For our purposes, a condition code mode is the same as SImode. */
if (mode == CCmode)
mode = SImode;
if (code0 == REG)
{
int regno0 = REGNO (op0) + subreg_word0;
@ -1017,13 +1058,16 @@ mips_move_1word (operands, insn, unsignedp)
ret = "mflo\t%0";
}
else if (ST_REG_P (regno1) && mips_isa >= 4)
ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
else
{
delay = DELAY_LOAD;
if (FP_REG_P (regno1))
ret = "mfc1\t%0,%1";
else if (regno1 == FPSW_REGNUM)
else if (regno1 == FPSW_REGNUM && mips_isa < 4)
ret = "cfc1\t%0,$31";
}
}
@ -1050,7 +1094,7 @@ mips_move_1word (operands, insn, unsignedp)
}
}
else if (regno0 == FPSW_REGNUM)
else if (regno0 == FPSW_REGNUM && mips_isa < 4)
{
if (GP_REG_P (regno1))
{
@ -1079,6 +1123,7 @@ mips_move_1word (operands, insn, unsignedp)
ret = "lw\t%0,%1";
break;
case SImode:
case CCmode:
ret = ((unsignedp && TARGET_64BIT)
? "lwu\t%0,%1"
: "lw\t%0,%1");
@ -1981,112 +2026,67 @@ gen_conditional_branch (operands, test_code)
rtx operands[];
enum rtx_code test_code;
{
static enum machine_mode mode_map[(int)CMP_MAX][(int)ITEST_MAX] = {
{ /* CMP_SI */
SImode, /* eq */
SImode, /* ne */
SImode, /* gt */
SImode, /* ge */
SImode, /* lt */
SImode, /* le */
SImode, /* gtu */
SImode, /* geu */
SImode, /* ltu */
SImode, /* leu */
},
{ /* CMP_DI */
DImode, /* eq */
DImode, /* ne */
DImode, /* gt */
DImode, /* ge */
DImode, /* lt */
DImode, /* le */
DImode, /* gtu */
DImode, /* geu */
DImode, /* ltu */
DImode, /* leu */
},
{ /* CMP_SF */
CC_FPmode, /* eq */
CC_REV_FPmode, /* ne */
CC_FPmode, /* gt */
CC_FPmode, /* ge */
CC_FPmode, /* lt */
CC_FPmode, /* le */
VOIDmode, /* gtu */
VOIDmode, /* geu */
VOIDmode, /* ltu */
VOIDmode, /* leu */
},
{ /* CMP_DF */
CC_FPmode, /* eq */
CC_REV_FPmode, /* ne */
CC_FPmode, /* gt */
CC_FPmode, /* ge */
CC_FPmode, /* lt */
CC_FPmode, /* le */
VOIDmode, /* gtu */
VOIDmode, /* geu */
VOIDmode, /* ltu */
VOIDmode, /* leu */
},
};
enum cmp_type type = branch_type;
rtx cmp0 = branch_cmp[0];
rtx cmp1 = branch_cmp[1];
enum machine_mode mode;
enum cmp_type type = branch_type;
rtx cmp0 = branch_cmp[0];
rtx cmp1 = branch_cmp[1];
rtx label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
rtx label2 = pc_rtx;
rtx reg = (rtx)0;
int invert = 0;
enum internal_test test = map_test_to_internal_test (test_code);
if (test == ITEST_MAX)
{
mode = word_mode;
goto fail;
}
/* Get the machine mode to use (CCmode, CC_EQmode, CC_FPmode, or CC_REV_FPmode). */
mode = mode_map[(int)type][(int)test];
if (mode == VOIDmode)
goto fail;
rtx reg;
int invert;
rtx label1, label2;
switch (type)
{
default:
goto fail;
abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
case CMP_SI:
case CMP_DI:
reg = gen_int_relational (test_code, (rtx)0, cmp0, cmp1, &invert);
if (reg != (rtx)0)
mode = type == CMP_SI ? SImode : DImode;
invert = FALSE;
reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
if (reg)
{
cmp0 = reg;
cmp1 = const0_rtx;
test_code = NE;
}
/* Make sure not non-zero constant if ==/!= */
else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
cmp1 = force_reg (mode, cmp1);
{
/* We don't want to build a comparison against a non-zero
constant. */
cmp1 = force_reg (mode, cmp1);
}
break;
case CMP_DF:
case CMP_SF:
{
rtx reg = gen_rtx (REG, mode, FPSW_REGNUM);
emit_insn (gen_rtx (SET, VOIDmode, reg, gen_rtx (test_code, mode, cmp0, cmp1)));
cmp0 = reg;
cmp1 = const0_rtx;
test_code = NE;
}
case CMP_DF:
if (mips_isa < 4)
reg = gen_rtx (REG, CCmode, FPSW_REGNUM);
else
reg = gen_reg_rtx (CCmode);
/* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
0 in the instruction built below. The MIPS FPU handles
inequality testing by testing for equality and looking for a
false result. */
emit_insn (gen_rtx (SET, VOIDmode,
reg,
gen_rtx (test_code == NE ? EQ : test_code,
CCmode, cmp0, cmp1)));
test_code = test_code == NE ? EQ : NE;
mode = CCmode;
cmp0 = reg;
cmp1 = const0_rtx;
invert = FALSE;
break;
}
/* Generate the jump */
/* Generate the branch. */
label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
label2 = pc_rtx;
if (invert)
{
label2 = label1;
@ -2099,13 +2099,102 @@ gen_conditional_branch (operands, test_code)
gen_rtx (test_code, mode, cmp0, cmp1),
label1,
label2)));
return;
fail:
abort_with_insn (gen_rtx (test_code, mode, cmp0, cmp1), "bad test");
}
/* Emit the common code for conditional moves. OPERANDS is the array
of operands passed to the conditional move defined_expand. */
void
gen_conditional_move (operands)
rtx *operands;
{
rtx op0 = branch_cmp[0];
rtx op1 = branch_cmp[1];
enum machine_mode mode = GET_MODE (branch_cmp[0]);
enum rtx_code cmp_code = GET_CODE (operands[1]);
enum rtx_code move_code = NE;
enum machine_mode op_mode = GET_MODE (operands[0]);
enum machine_mode cmp_mode;
rtx cmp_reg;
if (GET_MODE_CLASS (mode) != MODE_FLOAT)
{
switch (cmp_code)
{
case EQ:
cmp_code = XOR;
move_code = EQ;
break;
case NE:
cmp_code = XOR;
break;
case LT:
break;
case GE:
cmp_code = LT;
move_code = EQ;
break;
case GT:
cmp_code = LT;
op0 = force_reg (mode, branch_cmp[1]);
op1 = branch_cmp[0];
break;
case LE:
cmp_code = LT;
op0 = force_reg (mode, branch_cmp[1]);
op1 = branch_cmp[0];
move_code = EQ;
break;
case LTU:
break;
case GEU:
cmp_code = LTU;
move_code = EQ;
break;
case GTU:
cmp_code = LTU;
op0 = force_reg (mode, branch_cmp[1]);
op1 = branch_cmp[0];
break;
case LEU:
cmp_code = LTU;
op0 = force_reg (mode, branch_cmp[1]);
op1 = branch_cmp[0];
move_code = EQ;
break;
default:
abort ();
}
}
else
{
if (cmp_code == NE)
{
cmp_code = EQ;
move_code = EQ;
}
}
if (mode == SImode || mode == DImode)
cmp_mode = mode;
else if (mode == SFmode || mode == DFmode)
cmp_mode = CCmode;
else
abort ();
cmp_reg = gen_reg_rtx (cmp_mode);
emit_insn (gen_rtx (SET, cmp_mode,
cmp_reg,
gen_rtx (cmp_code, cmp_mode, op0, op1)));
emit_insn (gen_rtx (SET, op_mode,
operands[0],
gen_rtx (IF_THEN_ELSE, op_mode,
gen_rtx (move_code, VOIDmode,
cmp_reg,
CONST0_RTX (SImode)),
operands[2],
operands[3])));
}
#if 0
/* Internal code to generate the load and store of one word/short/byte.
@ -3443,6 +3532,11 @@ override_options ()
mips_cpu = PROCESSOR_R4650;
break;
case '5':
if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
mips_cpu = PROCESSOR_R5000;
break;
case '6':
if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
mips_cpu = PROCESSOR_R6000;
@ -3459,7 +3553,10 @@ override_options ()
break;
}
if (seen_v && mips_cpu != PROCESSOR_R4300 && mips_cpu != PROCESSOR_R4100)
if (seen_v
&& mips_cpu != PROCESSOR_R4300
&& mips_cpu != PROCESSOR_R4100
&& mips_cpu != PROCESSOR_R5000)
mips_cpu = PROCESSOR_DEFAULT;
if (mips_cpu == PROCESSOR_DEFAULT)
@ -3642,8 +3739,15 @@ override_options ()
{
register int temp;
if (mode == CC_FPmode || mode == CC_REV_FPmode)
temp = (regno == FPSW_REGNUM);
if (mode == CCmode)
{
if (mips_isa < 4)
temp = (regno == FPSW_REGNUM);
else
temp = (ST_REG_P (regno)
|| GP_REG_P (regno)
|| FP_REG_P (regno));
}
else if (GP_REG_P (regno))
temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
@ -3745,6 +3849,7 @@ mips_debugger_offset (addr, offset)
'b' print 'n' for EQ, 'z' for NE
'T' print 'f' for EQ, 't' for NE
't' print 't' for EQ, 'f' for NE
'Z' print register and a comma, but print nothing for $fcc0
'(' Turn on .set noreorder
')' Turn on .set reorder
'[' Turn on .set noat
@ -3935,6 +4040,19 @@ print_operand (file, op, letter)
assemble_name (file, buffer);
}
else if (letter == 'Z')
{
register int regnum;
if (code != REG)
abort ();
regnum = REGNO (op);
if (! ST_REG_P (regnum))
abort ();
if (regnum != ST_REG_FIRST)
fprintf (file, "%s,", reg_names[regnum]);
}
else if (code == REG)
{
register int regnum = REGNO (op);
@ -5853,5 +5971,26 @@ mips_secondary_reload_class (class, mode, x, in_p)
return GR_REGS;
}
/* We can only copy a value to a condition code register from a
floating point register, and even then we require a scratch
floating point register. We can only copy a value out of a
condition code register into a general register. */
if (class == ST_REGS)
{
if (in_p)
return FP_REGS;
if (GP_REG_P (regno))
return NO_REGS;
return GR_REGS;
}
if (ST_REG_P (regno))
{
if (! in_p)
return FP_REGS;
if (class == GR_REGS)
return NO_REGS;
return GR_REGS;
}
return NO_REGS;
}

111
gcc/config/mips/mips.h
View File

@ -70,6 +70,7 @@ enum processor_type {
PROCESSOR_R4300,
PROCESSOR_R4600,
PROCESSOR_R4650,
PROCESSOR_R5000,
PROCESSOR_R8000
};
@ -168,6 +169,7 @@ extern int function_arg_partial_nregs ();
extern void function_epilogue ();
extern void function_prologue ();
extern void gen_conditional_branch ();
extern void gen_conditional_move ();
extern struct rtx_def * gen_int_relational ();
extern void init_cumulative_args ();
extern int large_int ();
@ -555,6 +557,18 @@ do \
\
for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
else if (mips_isa < 4) \
{ \
int regno; \
\
/* We only have a single condition code register. We \
implement this by hiding all the condition code registers, \
and generating RTL that refers directly to ST_REG_FIRST. */ \
for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
fixed_regs[regno] = call_used_regs[regno] = 1; \
} \
SUBTARGET_CONDITIONAL_REGISTER_USAGE \
} \
@ -1200,14 +1214,16 @@ do { \
even those that are not normally considered general registers.
On the Mips, we have 32 integer registers, 32 floating point
registers and the special registers hi, lo, hilo, fp status, and rap.
The hilo register is only used in 64 bit mode. It represents a 64
bit value stored as two 32 bit values in the hi and lo registers;
this is the result of the mult instruction. rap is a pointer to the
stack where the return address reg ($31) was stored. This is needed
for C++ exception handling. */
registers, 8 condition code registers, and the special registers
hi, lo, hilo, and rap. The 8 condition code registers are only
used if mips_isa >= 4. The hilo register is only used in 64 bit
mode. It represents a 64 bit value stored as two 32 bit values in
the hi and lo registers; this is the result of the mult
instruction. rap is a pointer to the stack where the return
address reg ($31) was stored. This is needed for C++ exception
handling. */
#define FIRST_PSEUDO_REGISTER 69
#define FIRST_PSEUDO_REGISTER 76
/* 1 for registers that have pervasive standard uses
and are not available for the register allocator.
@ -1220,7 +1236,7 @@ do { \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 1, 1 \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
}
@ -1237,7 +1253,7 @@ do { \
0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1, 1, 1, 1, 1 \
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
}
@ -1260,21 +1276,25 @@ do { \
#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
#define ST_REG_FIRST 67
#define ST_REG_LAST 67
#define ST_REG_LAST 74
#define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
#define RAP_REG_NUM 68
#define RAP_REG_NUM 75
#define AT_REGNUM (GP_REG_FIRST + 1)
#define HI_REGNUM (MD_REG_FIRST + 0)
#define LO_REGNUM (MD_REG_FIRST + 1)
#define HILO_REGNUM (MD_REG_FIRST + 2)
/* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
mips_isa >= 4, it should not be used, and an arbitrary ST_REG
should be used instead. */
#define FPSW_REGNUM ST_REG_FIRST
#define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
#define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
#define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
#define ST_REG_P(REGNO) ((REGNO) == ST_REG_FIRST)
#define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
@ -1464,8 +1484,8 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
{ 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
{ 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
{ 0x00000000, 0x00000000, 0x00000008 }, /* status registers */ \
{ 0xffffffff, 0xffffffff, 0x0000000f } /* all registers */ \
{ 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
{ 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
}
@ -1625,7 +1645,8 @@ extern enum reg_class mips_char_to_class[];
|| (CLASS2 == GR_REGS && CLASS1 == FP_REGS))))
/* The HI and LO registers can only be reloaded via the general
registers. */
registers. Condition code registers can only be loaded to the
general registers, and from the floating point registers. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
mips_secondary_reload_class (CLASS, MODE, X, 1)
@ -2868,7 +2889,8 @@ while (0)
enum machine_mode xmode = GET_MODE (X); \
if (xmode == SFmode) \
{ \
if (mips_cpu == PROCESSOR_R3000) \
if (mips_cpu == PROCESSOR_R3000 \
|| mips_cpu == PROCESSOR_R5000) \
return COSTS_N_INSNS (4); \
else if (mips_cpu == PROCESSOR_R6000) \
return COSTS_N_INSNS (5); \
@ -2878,7 +2900,8 @@ while (0)
\
if (xmode == DFmode) \
{ \
if (mips_cpu == PROCESSOR_R3000) \
if (mips_cpu == PROCESSOR_R3000 \
|| mips_cpu == PROCESSOR_R5000) \
return COSTS_N_INSNS (5); \
else if (mips_cpu == PROCESSOR_R6000) \
return COSTS_N_INSNS (6); \
@ -2890,6 +2913,8 @@ while (0)
return COSTS_N_INSNS (12); \
else if (mips_cpu == PROCESSOR_R6000) \
return COSTS_N_INSNS (17); \
else if (mips_cpu == PROCESSOR_R5000) \
return COSTS_N_INSNS (5); \
else \
return COSTS_N_INSNS (10); \
} \
@ -2926,6 +2951,8 @@ while (0)
return COSTS_N_INSNS (35); \
else if (mips_cpu == PROCESSOR_R6000) \
return COSTS_N_INSNS (38); \
else if (mips_cpu == PROCESSOR_R5000) \
return COSTS_N_INSNS (36); \
else \
return COSTS_N_INSNS (69);
@ -3001,6 +3028,8 @@ while (0)
: (((TO) == HI_REG || (TO) == LO_REG \
|| (TO) == MD_REGS || (FROM) == HILO_REG) \
&& (FROM) == GR_REGS) ? 6 \
: (FROM) == ST_REGS && (TO) == GR_REGS ? 4 \
: (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
: 12)
/* ??? Fix this to be right for the R8000. */
@ -3053,6 +3082,7 @@ while (0)
{"small_int", { CONST_INT }}, \
{"large_int", { CONST_INT }}, \
{"mips_const_double_ok", { CONST_DOUBLE }}, \
{"const_float_1_operand", { CONST_DOUBLE }}, \
{"simple_memory_operand", { MEM, SUBREG }}, \
{"equality_op", { EQ, NE }}, \
{"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
@ -3082,40 +3112,6 @@ while (0)
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
final_prescan_insn (INSN, OPVEC, NOPERANDS)
/* Tell final.c how to eliminate redundant test instructions.
Here we define machine-dependent flags and fields in cc_status
(see `conditions.h'). */
/* A list of names to be used for additional modes for condition code
values in registers. These names are added to `enum machine_mode'
and all have class `MODE_CC'. By convention, they should start
with `CC' and end with `mode'.
You should only define this macro if your machine does not use
`cc0' and only if additional modes are required.
On the MIPS, we use CC_FPmode for all floating point except for not
equal, CC_REV_FPmode for not equal (to reverse the sense of the
jump), CC_EQmode for integer equality/inequality comparisons,
CC_0mode for comparisons against 0, and CCmode for other integer
comparisons. */
#define EXTRA_CC_MODES CC_EQmode, CC_FPmode, CC_0mode, CC_REV_FPmode
/* A list of C strings giving the names for the modes listed in
`EXTRA_CC_MODES'. */
#define EXTRA_CC_NAMES "CC_EQ", "CC_FP", "CC_0", "CC_REV_FP"
/* Returns a mode from class `MODE_CC' to be used when comparison
operation code OP is applied to rtx X. */
#define SELECT_CC_MODE(OP, X, Y) \
(GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
? SImode \
: ((OP == NE) ? CC_REV_FPmode : CC_FPmode))
/* Control the assembler format that we output. */
@ -3217,6 +3213,13 @@ while (0)
&mips_reg_names[66][0], \
&mips_reg_names[67][0], \
&mips_reg_names[68][0], \
&mips_reg_names[69][0], \
&mips_reg_names[70][0], \
&mips_reg_names[71][0], \
&mips_reg_names[72][0], \
&mips_reg_names[73][0], \
&mips_reg_names[74][0], \
&mips_reg_names[75][0], \
}
/* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
@ -3231,7 +3234,8 @@ while (0)
"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
"hi", "lo", "accum","$fcr31","$rap" \
"hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
"$fcc5","$fcc6","$fcc7","$rap" \
}
/* If defined, a C initializer for an array of structures
@ -3310,8 +3314,7 @@ while (0)
{ "fp", 30 + GP_REG_FIRST }, \
{ "ra", 31 + GP_REG_FIRST }, \
{ "$sp", 29 + GP_REG_FIRST }, \
{ "$fp", 30 + GP_REG_FIRST }, \
{ "cc", FPSW_REGNUM }, \
{ "$fp", 30 + GP_REG_FIRST } \
}
/* Define results of standard character escape sequences. */

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gcc/config/mips/mips.md
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