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[ARM] PR target/79911: Invalid vec_select arguments

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PR target/79911
	* config/arm/neon.md (vec_sel_widen_ssum_lo<VQI:mode><VW:mode>3):
	Rename to...
	(vec_sel_widen_ssum_lo<mode><V_half>3): ... This. Avoid mismatch
	between vec_select and vector argument.
	(vec_sel_widen_ssum_hi<VQI:mode><VW:mode>3): Rename to...
	(vec_sel_widen_ssum_hi<mode><V_half>3): ... This. Likewise.
	(vec_sel_widen_usum_lo<VQI:mode><VW:mode>3): Rename to...
	(vec_sel_widen_usum_lo<mode><V_half>3): ... This.
	(vec_sel_widen_usum_hi<VQI:mode><VW:mode>3): Rename to...
	(vec_sel_widen_usum_hi<mode><V_half>3): ... This.

From-SVN: r246084
This commit is contained in:
Kyrylo Tkachov 2017-03-13 10:58:48 +00:00 committed by Kyrylo Tkachov
parent 91cd87db7e
commit b8c3660369
2 changed files with 40 additions and 24 deletions
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14
gcc/ChangeLog
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@ -1,3 +1,17 @@
2017-03-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/79911
* config/arm/neon.md (vec_sel_widen_ssum_lo<VQI:mode><VW:mode>3):
Rename to...
(vec_sel_widen_ssum_lo<mode><V_half>3): ... This. Avoid mismatch
between vec_select and vector argument.
(vec_sel_widen_ssum_hi<VQI:mode><VW:mode>3): Rename to...
(vec_sel_widen_ssum_hi<mode><V_half>3): ... This. Likewise.
(vec_sel_widen_usum_lo<VQI:mode><VW:mode>3): Rename to...
(vec_sel_widen_usum_lo<mode><V_half>3): ... This.
(vec_sel_widen_usum_hi<VQI:mode><VW:mode>3): Rename to...
(vec_sel_widen_usum_hi<mode><V_half>3): ... This.
2017-03-13 Richard Biener <rguenther@suse.de>
PR other/79991

50
gcc/config/arm/neon.md
View File

@ -1335,14 +1335,14 @@
}
)
(define_insn "vec_sel_widen_ssum_lo<VQI:mode><VW:mode>3"
[(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w")
(plus:<VW:V_widen>
(sign_extend:<VW:V_widen>
(vec_select:VW
(define_insn "vec_sel_widen_ssum_lo<mode><V_half>3"
[(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
(plus:<V_double_width>
(sign_extend:<V_double_width>
(vec_select:<V_HALF>
(match_operand:VQI 1 "s_register_operand" "%w")
(match_operand:VQI 2 "vect_par_constant_low" "")))
(match_operand:<VW:V_widen> 3 "s_register_operand" "0")))]
(match_operand:<V_double_width> 3 "s_register_operand" "0")))]
"TARGET_NEON"
{
return BYTES_BIG_ENDIAN ? "vaddw.<V_s_elem>\t%q0, %q3, %f1" :
@ -1350,13 +1350,14 @@
}
[(set_attr "type" "neon_add_widen")])
(define_insn "vec_sel_widen_ssum_hi<VQI:mode><VW:mode>3"
[(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w")
(plus:<VW:V_widen>
(sign_extend:<VW:V_widen>
(vec_select:VW (match_operand:VQI 1 "s_register_operand" "%w")
(define_insn "vec_sel_widen_ssum_hi<mode><V_half>3"
[(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
(plus:<V_double_width>
(sign_extend:<V_double_width>
(vec_select:<V_HALF>
(match_operand:VQI 1 "s_register_operand" "%w")
(match_operand:VQI 2 "vect_par_constant_high" "")))
(match_operand:<VW:V_widen> 3 "s_register_operand" "0")))]
(match_operand:<V_double_width> 3 "s_register_operand" "0")))]
"TARGET_NEON"
{
return BYTES_BIG_ENDIAN ? "vaddw.<V_s_elem>\t%q0, %q3, %e1" :
@ -1404,14 +1405,14 @@
}
)
(define_insn "vec_sel_widen_usum_lo<VQI:mode><VW:mode>3"
[(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w")
(plus:<VW:V_widen>
(zero_extend:<VW:V_widen>
(vec_select:VW
(define_insn "vec_sel_widen_usum_lo<mode><V_half>3"
[(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
(plus:<V_double_width>
(zero_extend:<V_double_width>
(vec_select:<V_HALF>
(match_operand:VQI 1 "s_register_operand" "%w")
(match_operand:VQI 2 "vect_par_constant_low" "")))
(match_operand:<VW:V_widen> 3 "s_register_operand" "0")))]
(match_operand:<V_double_width> 3 "s_register_operand" "0")))]
"TARGET_NEON"
{
return BYTES_BIG_ENDIAN ? "vaddw.<V_u_elem>\t%q0, %q3, %f1" :
@ -1419,13 +1420,14 @@
}
[(set_attr "type" "neon_add_widen")])
(define_insn "vec_sel_widen_usum_hi<VQI:mode><VW:mode>3"
[(set (match_operand:<VW:V_widen> 0 "s_register_operand" "=w")
(plus:<VW:V_widen>
(zero_extend:<VW:V_widen>
(vec_select:VW (match_operand:VQI 1 "s_register_operand" "%w")
(define_insn "vec_sel_widen_usum_hi<mode><V_half>3"
[(set (match_operand:<V_double_width> 0 "s_register_operand" "=w")
(plus:<V_double_width>
(zero_extend:<V_double_width>
(vec_select:<V_HALF>
(match_operand:VQI 1 "s_register_operand" "%w")
(match_operand:VQI 2 "vect_par_constant_high" "")))
(match_operand:<VW:V_widen> 3 "s_register_operand" "0")))]
(match_operand:<V_double_width> 3 "s_register_operand" "0")))]
"TARGET_NEON"
{
return BYTES_BIG_ENDIAN ? "vaddw.<V_u_elem>\t%q0, %q3, %e1" :