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aarch64: Add support for unpacked SVE shifts
This patch adds support for unpacked SVE LSL, ASR and LSR. For right shifts, the type suffix needs to be taken from the element size rather than the container size. gcc/ * config/aarch64/aarch64-sve.md (<ASHIFT:optab><mode>3) (v<ASHIFT:optab><mode>3, @aarch64_pred_<optab><mode>) (*post_ra_v<ASHIFT:optab><mode>3): Extend from SVE_FULL_I to SVE_I. gcc/testsuite/ * gcc.target/aarch64/sve/shift_2.c: New test.
This commit is contained in:
Richard Sandiford
parent
cbe9758ff4
commit
b81fbfe1eb
@ -4500,9 +4500,9 @@
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;; Unpredicated shift by a scalar, which expands into one of the vector
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;; shifts below.
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(define_expand "<ASHIFT:optab><mode>3"
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[(set (match_operand:SVE_FULL_I 0 "register_operand")
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(ASHIFT:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand")
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[(set (match_operand:SVE_I 0 "register_operand")
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(ASHIFT:SVE_I
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(match_operand:SVE_I 1 "register_operand")
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(match_operand:<VEL> 2 "general_operand")))]
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"TARGET_SVE"
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{
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@ -4527,12 +4527,12 @@
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;; Unpredicated shift by a vector.
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(define_expand "v<optab><mode>3"
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[(set (match_operand:SVE_FULL_I 0 "register_operand")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand")
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(unspec:SVE_I
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[(match_dup 3)
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(ASHIFT:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand")
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(match_operand:SVE_FULL_I 2 "aarch64_sve_<lr>shift_operand"))]
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(ASHIFT:SVE_I
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(match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_I 2 "aarch64_sve_<lr>shift_operand"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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{
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@ -4545,12 +4545,12 @@
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;; likely to gain much and would make the instruction seem less uniform
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;; to the register allocator.
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(define_insn_and_split "@aarch64_pred_<optab><mode>"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, w, ?&w")
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(unspec:SVE_FULL_I
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, w, ?&w")
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
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(ASHIFT:SVE_FULL_I
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(match_operand:SVE_FULL_I 2 "register_operand" "w, 0, w, w")
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(match_operand:SVE_FULL_I 3 "aarch64_sve_<lr>shift_operand" "D<lr>, w, 0, w"))]
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(ASHIFT:SVE_I
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(match_operand:SVE_I 2 "register_operand" "w, 0, w, w")
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(match_operand:SVE_I 3 "aarch64_sve_<lr>shift_operand" "D<lr>, w, 0, w"))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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"@
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@ -4560,7 +4560,7 @@
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movprfx\t%0, %2\;<shift>\t%0.<Vetype>, %1/m, %0.<Vetype>, %3.<Vetype>"
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"&& reload_completed
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&& !register_operand (operands[3], <MODE>mode)"
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[(set (match_dup 0) (ASHIFT:SVE_FULL_I (match_dup 2) (match_dup 3)))]
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[(set (match_dup 0) (ASHIFT:SVE_I (match_dup 2) (match_dup 3)))]
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""
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[(set_attr "movprfx" "*,*,*,yes")]
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)
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@ -4569,10 +4569,10 @@
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;; These are generated by splitting a predicated instruction whose
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;; predicate is unused.
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(define_insn "*post_ra_v<optab><mode>3"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w")
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(ASHIFT:SVE_FULL_I
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(match_operand:SVE_FULL_I 1 "register_operand" "w")
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(match_operand:SVE_FULL_I 2 "aarch64_simd_<lr>shift_imm")))]
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[(set (match_operand:SVE_I 0 "register_operand" "=w")
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(ASHIFT:SVE_I
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(match_operand:SVE_I 1 "register_operand" "w")
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(match_operand:SVE_I 2 "aarch64_simd_<lr>shift_imm")))]
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"TARGET_SVE && reload_completed"
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"<shift>\t%0.<Vetype>, %1.<Vetype>, #%2"
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)
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81
gcc/testsuite/gcc.target/aarch64/sve/shift_2.c
Normal file
81
gcc/testsuite/gcc.target/aarch64/sve/shift_2.c
Normal file
@ -0,0 +1,81 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_SHIFT_IMM(TYPE, NAME, OP, AMT) \
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TYPE NAME##_##TYPE##_##AMT (TYPE a) { return a OP AMT; }
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#define TEST_SHIFT(TYPE, NAME, OP, LIMIT) \
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TYPE NAME##_##TYPE##_reg (TYPE a, TYPE b) { return a OP b; } \
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TEST_SHIFT_IMM (TYPE, NAME, OP, 1) \
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TEST_SHIFT_IMM (TYPE, NAME, OP, 5) \
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TEST_SHIFT_IMM (TYPE, NAME, OP, LIMIT)
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#define TEST_TYPE(TYPE, SIZE, LIMIT) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_SHIFT (TYPE##SIZE, shl, <<, LIMIT) \
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TEST_SHIFT (TYPE##SIZE, shr, >>, LIMIT) \
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TEST_TYPE (int8_t, 32, 7)
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TEST_TYPE (uint8_t, 32, 7)
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TEST_TYPE (int8_t, 64, 7)
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TEST_TYPE (uint8_t, 64, 7)
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TEST_TYPE (int16_t, 64, 15)
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TEST_TYPE (uint16_t, 64, 15)
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TEST_TYPE (int8_t, 128, 7)
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TEST_TYPE (uint8_t, 128, 7)
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TEST_TYPE (int16_t, 128, 15)
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TEST_TYPE (uint16_t, 128, 15)
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TEST_TYPE (int32_t, 128, 31)
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TEST_TYPE (uint32_t, 128, 31)
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 6 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 6 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 4 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #1\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.s, z[0-9]+\.s, #1\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.b, z[0-9]+\.b, #1\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.h, z[0-9]+\.h, #1\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.s, z[0-9]+\.s, #1\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 6 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #5\n} 4 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #5\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.h, z[0-9]+\.h, #5\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.s, z[0-9]+\.s, #5\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.h, z[0-9]+\.h, #5\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.s, z[0-9]+\.s, #5\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b, z[0-9]+\.b, #7\n} 6 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h, z[0-9]+\.h, #15\n} 4 } } */
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/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.s, z[0-9]+\.s, #31\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.b, z[0-9]+\.b, #7\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.h, z[0-9]+\.h, #15\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tlsr\tz[0-9]+\.s, z[0-9]+\.s, #31\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.b, z[0-9]+\.b, #7\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.h, z[0-9]+\.h, #15\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tasr\tz[0-9]+\.s, z[0-9]+\.s, #31\n} 1 } } */
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