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add scheduling information for stores
From-SVN: r11481
This commit is contained in:
David Edelsohn
parent
1ec26da6f1
commit
b7ff3d825a
@ -23,7 +23,7 @@
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;; Define an insn type attribute. This is used in function unit delay
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;; computations.
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(define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
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(define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
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(const_string "integer"))
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;; Length (in bytes).
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@ -40,17 +40,27 @@
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;; Processor type -- this attribute must exactly match the processor_type
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;; enumeration in rs6000.h.
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(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc602,ppc603,ppc604,ppc620"
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(define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"
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(const (symbol_ref "rs6000_cpu_attr")))
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; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
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; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
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; Load/Store Unit -- POWER/2 and pure PowerPC only
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; Load/Store Unit -- pure PowerPC only
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; (POWER and 601 use Integer Unit)
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(define_function_unit "lsu" 1 0
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "mpccore,ppc602,ppc603,ppc604,ppc620"))
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(eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
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2 1)
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(define_function_unit "lsu" 1 0
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(and (eq_attr "type" "store,fpstore")
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(eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
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1 1)
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(define_function_unit "lsu" 1 0
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "mpccore,ppc603"))
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2 1)
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(define_function_unit "lsu" 1 0
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@ -58,27 +68,46 @@
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(eq_attr "cpu" "ppc604,ppc620"))
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3 1)
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(define_function_unit "lsu" 1 0
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "mpccore,ppc602,ppc603"))
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2 1)
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "load")
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(eq_attr "cpu" "rios1,ppc601,ppc403"))
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(eq_attr "cpu" "rios1,ppc403,ppc601"))
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2 1)
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "store,fpstore")
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(eq_attr "cpu" "rios1,ppc403,ppc601"))
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1 1)
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "fpstore")
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(eq_attr "cpu" "rios1,ppc601"))
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0 1)
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "rios1"))
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2 1)
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "fpload")
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(eq_attr "cpu" "rios1,ppc601"))
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2 0)
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(eq_attr "cpu" "ppc601"))
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3 1)
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(define_function_unit "iu2" 2 0
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(and (eq_attr "type" "load,fpload")
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(eq_attr "cpu" "rios2"))
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2 1)
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(define_function_unit "iu2" 2 0
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(and (eq_attr "type" "store,fpstore")
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(eq_attr "cpu" "rios2"))
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1 1)
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; Integer Unit (RIOS1, PPC601, PPC603)
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; Trivial operations take one cycle which need not be listed here.
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "imul")
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(eq_attr "cpu" "rios1"))
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3 3)
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(and (eq_attr "type" "integer")
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(eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
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1 1)
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "imul")
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@ -87,7 +116,7 @@
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "imul")
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(eq_attr "cpu" "ppc601,ppc602,ppc603"))
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(eq_attr "cpu" "rios1,ppc601,ppc603"))
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5 5)
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(define_function_unit "iu" 1 0
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@ -95,11 +124,6 @@
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(eq_attr "cpu" "rios1"))
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19 19)
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc601"))
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36 36)
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc403"))
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@ -107,7 +131,12 @@
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc602,ppc603"))
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(eq_attr "cpu" "ppc601"))
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36 36)
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc603"))
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37 36)
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; RIOS2 has two integer units: a primary one which can perform all
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@ -118,7 +147,7 @@
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(define_function_unit "iu2" 2 0
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(and (eq_attr "type" "integer")
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(eq_attr "cpu" "rios2"))
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1 0)
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1 1)
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(define_function_unit "iu2" 2 0
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(and (eq_attr "type" "imul")
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@ -135,7 +164,6 @@
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(eq_attr "cpu" "rios2"))
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2 2)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "rios2"))
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@ -159,20 +187,17 @@
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(define_function_unit "iu2" 2 0
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(and (eq_attr "type" "integer")
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(eq_attr "cpu" "ppc604,ppc620"))
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1 1
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[(eq_attr "type" "imul,idiv")])
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1 1)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "imul")
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(eq_attr "cpu" "ppc604,ppc620"))
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4 2
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[(eq_attr "type" "integer")])
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4 2)
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(define_function_unit "imuldiv" 1 0
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(and (eq_attr "type" "idiv")
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(eq_attr "cpu" "ppc604,ppc620"))
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20 19
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[(eq_attr "type" "integer")])
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20 19)
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; compare is done on integer unit, but feeds insns which
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; execute on the branch unit. Ready-delay of the compare
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@ -182,36 +207,34 @@
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; able to fill the compare-branch delay, with insns on iu/fpu.
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "compare")
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(eq_attr "cpu" "rios1,mpccore,ppc601"))
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1 1)
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(define_function_unit "iu2" 2 0
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(and (eq_attr "type" "compare")
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(eq_attr "cpu" "rios2"))
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1 1)
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(define_function_unit "bpu" 1 0
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(and (eq_attr "type" "compare")
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(eq_attr "cpu" "rios1,rios2,ppc403,mpccore,ppc601,ppc603,ppc604,ppc620"))
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(eq_attr "cpu" "rios1"))
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4 1)
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; different machines have different compare timings
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; in ppc604, compare is done on the one of the two
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; main integer units.
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "delayed_compare")
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(eq_attr "cpu" "rios1"))
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5 1)
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "compare,delayed_compare")
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(eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
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3 1)
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(define_function_unit "iu2" 2 0
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(and (eq_attr "type" "compare,delayed_compare")
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(eq_attr "cpu" "rios2"))
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3 1)
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(define_function_unit "iu2" 2 0
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(and (eq_attr "type" "compare")
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(and (eq_attr "type" "compare,delayed_compare")
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(eq_attr "cpu" "ppc604,ppc620"))
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1 1)
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(define_function_unit "bpu" 1 0
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(eq_attr "type" "delayed_compare")
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5 0)
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; fp compare uses fp unit
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "rios1"))
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8 1)
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9 1)
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; rios1 and rios2 have different fpcompare delays
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(define_function_unit "fpu2" 2 0
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@ -222,16 +245,16 @@
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; on ppc601 and ppc603, fpcompare takes also 2 cycles from
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; the integer unit
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; here we do not define delays, just occupy the unit. The dependencies
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; will be signed by the fpcompare definition in the fpu.
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; will be assigned by the fpcompare definition in the fpu.
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(define_function_unit "iu" 1 0
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppc601,ppc602,ppc603"))
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(eq_attr "cpu" "ppc601,ppc603"))
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0 2)
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; fp compare uses fp unit
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "fpcompare")
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(eq_attr "cpu" "ppc601,ppc602,ppc603,ppc604,ppc620"))
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(eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
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5 1)
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(define_function_unit "fpu" 1 0
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@ -242,27 +265,27 @@
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(define_function_unit "bpu" 1 0
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "rios1,rios2"))
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5 0)
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5 1)
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(define_function_unit "bpu" 1 0
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(and (eq_attr "type" "mtjmpr")
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(eq_attr "cpu" "ppc403,mpccore,ppc601,ppc602,ppc603,ppc604,ppc620"))
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4 0)
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(eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
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4 1)
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; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
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(define_function_unit "bpu" 1 0
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(eq_attr "type" "jmpreg")
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1 0)
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1 1)
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(define_function_unit "bpu" 1 0
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(eq_attr "type" "branch")
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1 0)
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1 1)
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; Floating Point Unit
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "fp,dmul")
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(eq_attr "cpu" "rios1"))
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2 0)
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2 1)
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "fp")
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@ -272,11 +295,11 @@
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppc601"))
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4 0)
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4 1)
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "ppc602,ppc603,ppc604,ppc620"))
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(eq_attr "cpu" "ppc603,ppc604,ppc620"))
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3 1)
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(define_function_unit "fpu" 1 0
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@ -292,7 +315,7 @@
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; is this true?
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "ppc602,ppc603"))
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(eq_attr "cpu" "ppc603"))
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4 2)
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(define_function_unit "fpu" 1 0
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@ -317,7 +340,7 @@
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "sdiv")
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(eq_attr "cpu" "ppc602,ppc603,ppc604,ppc620"))
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(eq_attr "cpu" "ppc603,ppc604,ppc620"))
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18 18)
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(define_function_unit "fpu" 1 0
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@ -332,7 +355,7 @@
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(define_function_unit "fpu" 1 0
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(and (eq_attr "type" "ddiv")
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(eq_attr "cpu" "ppc602,ppc603"))
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(eq_attr "cpu" "ppc603"))
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33 33)
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(define_function_unit "fpu" 1 0
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@ -349,12 +372,12 @@
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(define_function_unit "fpu2" 2 0
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(and (eq_attr "type" "fp")
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(eq_attr "cpu" "rios2"))
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2 0)
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2 1)
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(define_function_unit "fpu2" 2 0
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(and (eq_attr "type" "dmul")
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(eq_attr "cpu" "rios2"))
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2 0)
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2 1)
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(define_function_unit "fpu2" 2 0
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(and (eq_attr "type" "sdiv,ddiv")
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@ -1570,7 +1593,8 @@
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(const_int 32))))
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(clobber (match_scratch:SI 0 "=l"))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __mulh")
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"bla __mulh"
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[(set_attr "type" "imul")])
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(define_insn "mull_call"
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[(set (reg:DI 3)
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@ -1579,7 +1603,8 @@
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(clobber (match_scratch:SI 0 "=l"))
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(clobber (reg:SI 0))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __mull")
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"bla __mull"
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[(set_attr "type" "imul")])
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(define_insn "divss_call"
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[(set (reg:SI 3)
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@ -1589,7 +1614,8 @@
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(clobber (match_scratch:SI 0 "=l"))
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(clobber (reg:SI 0))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __divss")
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"bla __divss"
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[(set_attr "type" "idiv")])
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(define_insn "divus_call"
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[(set (reg:SI 3)
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@ -1601,14 +1627,16 @@
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(clobber (match_scratch:CC 1 "=x"))
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(clobber (reg:CC 69))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __divus")
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"bla __divus"
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[(set_attr "type" "idiv")])
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(define_insn "quoss_call"
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[(set (reg:SI 3)
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(div:SI (reg:SI 3) (reg:SI 4)))
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(clobber (match_scratch:SI 0 "=l"))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __quoss")
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"bla __quoss"
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[(set_attr "type" "idiv")])
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(define_insn "quous_call"
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[(set (reg:SI 3)
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@ -1618,7 +1646,8 @@
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(clobber (match_scratch:CC 1 "=x"))
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(clobber (reg:CC 69))]
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"! TARGET_POWER && ! TARGET_POWERPC"
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"bla __quous")
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"bla __quous"
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[(set_attr "type" "idiv")])
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(define_insn "andsi3"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
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@ -4941,7 +4970,7 @@
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mt%0 %1
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mt%0 %1
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cror 0,0,0"
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[(set_attr "type" "*,load,load,*,load,*,*,*,*,*,*,*,mtjmpr,*")
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[(set_attr "type" "*,load,load,*,load,store,*,*,*,*,*,*,mtjmpr,*")
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(set_attr "length" "4,4,4,4,4,4,4,4,8,4,4,4,4,4")])
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;; Split a load of a large constant into the appropriate two-insn
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@ -5006,7 +5035,7 @@
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mt%0 %1
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mt%0 %1
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cror 0,0,0"
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[(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
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[(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
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|
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(define_expand "movqi"
|
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[(set (match_operand:QI 0 "general_operand" "")
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@ -5041,7 +5070,7 @@
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mt%0 %1
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mt%0 %1
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cror 0,0,0"
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[(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
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[(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
|
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|
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;; Here is how to move condition codes around. When we store CC data in
|
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;; an integer register or memory, we store just the high-order 4 bits.
|
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@ -5066,7 +5095,7 @@
|
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mr %0,%1
|
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{l%U1%X1|lwz%U1%X1} %0,%1
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{st%U0%U1|stw%U0%U1} %1,%0"
|
||||
[(set_attr "type" "*,*,*,compare,*,*,load,*")
|
||||
[(set_attr "type" "*,*,*,compare,*,*,load,store")
|
||||
(set_attr "length" "*,*,12,*,8,*,*,*")])
|
||||
|
||||
;; For floating-point, we normally deal with the floating-point registers
|
||||
@ -5199,7 +5228,7 @@
|
||||
fmr %0,%1
|
||||
lfs%U1%X1 %0,%1
|
||||
stfs%U0%X0 %1,%0"
|
||||
[(set_attr "type" "fp,fpload,*")])
|
||||
[(set_attr "type" "fp,fpload,fpstore")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
|
||||
@ -5213,7 +5242,7 @@
|
||||
{lil|li} %0,%1
|
||||
{liu|lis} %0,%u1
|
||||
{cal|la} %0,%1(%*)"
|
||||
[(set_attr "type" "*,load,*,*,*,*")])
|
||||
[(set_attr "type" "*,load,store,*,*,*")])
|
||||
|
||||
|
||||
(define_expand "movdf"
|
||||
@ -5317,7 +5346,7 @@
|
||||
return \"stfd%U0%X0 %1,%0\";
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "*,load,*,*,fp,fpload,*")
|
||||
[(set_attr "type" "*,load,store,*,fp,fpload,fpstore")
|
||||
(set_attr "length" "8,8,8,8,*,*,*")])
|
||||
|
||||
(define_insn ""
|
||||
@ -5354,7 +5383,7 @@
|
||||
return \"#\";
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "*,load,*,*")
|
||||
[(set_attr "type" "*,load,store,*")
|
||||
(set_attr "length" "8,8,8,8")])
|
||||
|
||||
(define_insn ""
|
||||
@ -5371,7 +5400,7 @@
|
||||
fmr %0,%1
|
||||
lfd%U1%X1 %0,%1
|
||||
stfd%U0%X0 %1,%0"
|
||||
[(set_attr "type" "*,load,*,*,fp,fpload,*")])
|
||||
[(set_attr "type" "*,load,store,*,fp,fpload,fpstore")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
|
||||
@ -5384,7 +5413,7 @@
|
||||
ld%U1%X1 %0,%1
|
||||
std%U0%X0 %1,%0
|
||||
#"
|
||||
[(set_attr "type" "*,load,*,*")])
|
||||
[(set_attr "type" "*,load,store,*")])
|
||||
|
||||
;; Next come the multi-word integer load and store and the load and store
|
||||
;; multiple insns.
|
||||
@ -5513,7 +5542,7 @@
|
||||
return \"stfd%U0%X0 %1,%0\";
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "*,load,*,fp,fpload,*")
|
||||
[(set_attr "type" "*,load,store,fp,fpload,fpstore")
|
||||
(set_attr "length" "8,8,8,*,*,*")])
|
||||
|
||||
(define_insn ""
|
||||
@ -5535,7 +5564,7 @@
|
||||
mf%1 %0
|
||||
mt%0 %1
|
||||
cror 0,0,0"
|
||||
[(set_attr "type" "*,load,*,*,*,*,*,fp,fpload,*,*,mtjmpr,*")
|
||||
[(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
|
||||
(set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
|
||||
|
||||
;; Split a load of a large constant into the appropriate five-instruction
|
||||
@ -5684,7 +5713,7 @@
|
||||
return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "*,load,load,*,*")
|
||||
[(set_attr "type" "store,store,*,load,load")
|
||||
(set_attr "length" "*,16,16,*,16")])
|
||||
|
||||
(define_insn ""
|
||||
@ -5729,7 +5758,7 @@
|
||||
return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "load,*,*")
|
||||
[(set_attr "type" "store,*,load")
|
||||
(set_attr "length" "16,16,16")])
|
||||
|
||||
(define_insn ""
|
||||
@ -5763,7 +5792,7 @@
|
||||
return \"std%U0 %1,%0\;std %L1,%L0\";
|
||||
}
|
||||
}"
|
||||
[(set_attr "type" "*,load,*")
|
||||
[(set_attr "type" "*,load,store")
|
||||
(set_attr "length" "8,8,8")])
|
||||
|
||||
(define_expand "load_multiple"
|
||||
@ -5858,8 +5887,8 @@
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "32")])
|
||||
|
||||
|
||||
|
||||
(define_expand "store_multiple"
|
||||
[(match_par_dup 3 [(set (match_operand:SI 0 "" "")
|
||||
(match_operand:SI 1 "" ""))
|
||||
@ -5908,7 +5937,8 @@
|
||||
(match_operand:SI 2 "gpc_reg_operand" "r"))
|
||||
(clobber (match_scratch:SI 3 "=q"))])]
|
||||
"TARGET_STRING && TARGET_POWER"
|
||||
"{stsi|stswi} %2,%P1,%O0")
|
||||
"{stsi|stswi} %2,%P1,%O0"
|
||||
[(set_attr "type" "store")])
|
||||
|
||||
(define_insn ""
|
||||
[(match_parallel 0 "store_multiple_operation"
|
||||
@ -5916,7 +5946,8 @@
|
||||
(match_operand:SI 2 "gpc_reg_operand" "r"))
|
||||
(clobber (match_scratch:SI 3 "X"))])]
|
||||
"TARGET_STRING && !TARGET_POWER"
|
||||
"{stsi|stswi} %2,%1,%O0")
|
||||
"{stsi|stswi} %2,%1,%O0"
|
||||
[(set_attr "type" "store")])
|
||||
|
||||
|
||||
;; String/block move insn.
|
||||
@ -5978,7 +6009,8 @@
|
||||
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
|
||||
&& REGNO (operands[4]) == 5"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
|
||||
@ -6000,7 +6032,8 @@
|
||||
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
|
||||
&& REGNO (operands[4]) == 5"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Move up to 24 bytes at a time. The fixed registers are needed because the
|
||||
;; register allocator doesn't have a clue about allocating 6 word registers
|
||||
@ -6037,7 +6070,8 @@
|
||||
&& (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
|
||||
&& REGNO (operands[4]) == 7"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
|
||||
@ -6057,7 +6091,8 @@
|
||||
&& (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
|
||||
&& REGNO (operands[4]) == 7"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
|
||||
;; with TImode
|
||||
@ -6090,7 +6125,8 @@
|
||||
&& (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
|
||||
&& REGNO (operands[4]) == 9"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
|
||||
@ -6108,7 +6144,8 @@
|
||||
&& (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
|
||||
&& REGNO (operands[4]) == 9"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Move up to 8 bytes at a time.
|
||||
(define_expand "movstrsi_2reg"
|
||||
@ -6131,7 +6168,8 @@
|
||||
"TARGET_STRING && TARGET_POWER && !TARGET_64BIT
|
||||
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
|
||||
@ -6143,7 +6181,8 @@
|
||||
"TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
|
||||
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Move up to 4 bytes at a time.
|
||||
(define_expand "movstrsi_1reg"
|
||||
@ -6166,7 +6205,8 @@
|
||||
"TARGET_STRING && TARGET_POWER
|
||||
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
|
||||
@ -6178,7 +6218,8 @@
|
||||
"TARGET_STRING && !TARGET_POWER
|
||||
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
|
||||
;; Define insns that do load or store with update. Some of these we can
|
||||
@ -6222,7 +6263,8 @@
|
||||
"TARGET_POWERPC64"
|
||||
"@
|
||||
stdux %3,%0,%2
|
||||
stdu %3,%2(%0)")
|
||||
stdu %3,%2(%0)"
|
||||
[(set_attr "type" "store")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
|
||||
@ -6245,7 +6287,8 @@
|
||||
""
|
||||
"@
|
||||
{stux|stwux} %3,%0,%2
|
||||
{stu|stwu} %3,%2(%0)")
|
||||
{stu|stwu} %3,%2(%0)"
|
||||
[(set_attr "type" "store")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
|
||||
@ -6294,7 +6337,8 @@
|
||||
""
|
||||
"@
|
||||
sthux %3,%0,%2
|
||||
sthu %3,%2(%0)")
|
||||
sthu %3,%2(%0)"
|
||||
[(set_attr "type" "store")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
|
||||
@ -6330,7 +6374,8 @@
|
||||
""
|
||||
"@
|
||||
stbux %3,%0,%2
|
||||
stbu %3,%2(%0)")
|
||||
stbu %3,%2(%0)"
|
||||
[(set_attr "type" "store")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
|
||||
@ -6353,7 +6398,8 @@
|
||||
"TARGET_HARD_FLOAT"
|
||||
"@
|
||||
stfsux %3,%0,%2
|
||||
stfsu %3,%2(%0)")
|
||||
stfsu %3,%2(%0)"
|
||||
[(set_attr "type" "fpstore")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
|
||||
@ -6376,7 +6422,8 @@
|
||||
"TARGET_HARD_FLOAT"
|
||||
"@
|
||||
stfdux %3,%0,%2
|
||||
stfdu %3,%2(%0)")
|
||||
stfdu %3,%2(%0)"
|
||||
[(set_attr "type" "fpstore")])
|
||||
|
||||
;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
|
||||
|
||||
@ -6520,8 +6567,8 @@
|
||||
emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
|
||||
|
||||
;; A function pointer under AIX is a pointer to a data area whose first word
|
||||
;; contains the actual address of the function, whose second word contains a
|
||||
;; pointer to its TOC, and whose third word contains a value to place in the
|
||||
@ -6550,7 +6597,8 @@
|
||||
"DEFAULT_ABI == ABI_AIX
|
||||
&& (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
|
||||
"{st|stw} %4,%a3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%a3"
|
||||
[(set_attr "length" "28")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "28")])
|
||||
|
||||
(define_insn "call_value_indirect_aix"
|
||||
[(set (match_operand 0 "register_operand" "fg")
|
||||
@ -6565,7 +6613,8 @@
|
||||
"DEFAULT_ABI == ABI_AIX
|
||||
&& (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
|
||||
"{st|stw} %5,%a4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1);\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%a4"
|
||||
[(set_attr "length" "28")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "28")])
|
||||
|
||||
;; A function pointer undef NT is a pointer to a data area whose first word
|
||||
;; contains the actual address of the function, whose second word contains a
|
||||
@ -6592,7 +6641,8 @@
|
||||
"DEFAULT_ABI == ABI_NT
|
||||
&& (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
|
||||
"{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3"
|
||||
[(set_attr "length" "24")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "24")])
|
||||
|
||||
(define_insn "call_value_indirect_nt"
|
||||
[(set (match_operand 0 "register_operand" "fg")
|
||||
@ -6606,7 +6656,8 @@
|
||||
"DEFAULT_ABI == ABI_NT
|
||||
&& (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
|
||||
"{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4"
|
||||
[(set_attr "length" "24")])
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "24")])
|
||||
|
||||
;; A function pointer under System V is just a normal pointer
|
||||
;; operands[0] is the function pointer
|
||||
@ -6629,7 +6680,8 @@
|
||||
|
||||
return \"{brl|blrl}\";
|
||||
}"
|
||||
[(set_attr "length" "4,8")])
|
||||
[(set_attr "type" "jmpreg")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_insn "call_value_indirect_sysv"
|
||||
[(set (match_operand 0 "register_operand" "=fg,fg")
|
||||
@ -6648,7 +6700,8 @@
|
||||
|
||||
return \"{brl|blrl}\";
|
||||
}"
|
||||
[(set_attr "length" "4,8")])
|
||||
[(set_attr "type" "jmpreg")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
;; Now the definitions for the call and call_value insns
|
||||
(define_expand "call"
|
||||
@ -6792,7 +6845,8 @@
|
||||
|
||||
return \"bl %z0\";
|
||||
}"
|
||||
[(set_attr "length" "4,8")])
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
;; Call to function which may be in another module. Restore the TOC
|
||||
;; pointer (r2) after the call unless this is System V.
|
||||
@ -6822,7 +6876,8 @@
|
||||
|
||||
return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
|
||||
}"
|
||||
[(set_attr "length" "8,12")])
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "length" "8,12")])
|
||||
|
||||
(define_insn ""
|
||||
[(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
|
||||
@ -6845,7 +6900,8 @@
|
||||
|
||||
return \"bl %z0\";
|
||||
}"
|
||||
[(set_attr "length" "4,8")])
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand 0 "" "=fg,fg")
|
||||
@ -6864,7 +6920,8 @@
|
||||
|
||||
return \"bl %z1\";
|
||||
}"
|
||||
[(set_attr "length" "4,8")])
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand 0 "" "=fg,fg")
|
||||
@ -6888,7 +6945,8 @@
|
||||
|
||||
return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
|
||||
}"
|
||||
[(set_attr "length" "8,12")])
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "length" "8,12")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand 0 "" "=fg,fg")
|
||||
@ -6912,11 +6970,10 @@
|
||||
|
||||
return \"bl %z1\";
|
||||
}"
|
||||
[(set_attr "length" "4,8")])
|
||||
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
;; Call subroutine returning any type.
|
||||
|
||||
(define_expand "untyped_call"
|
||||
[(parallel [(call (match_operand 0 "" "")
|
||||
(const_int 0))
|
||||
@ -8590,7 +8647,8 @@
|
||||
(pc)))]
|
||||
"direct_return ()"
|
||||
"{%C0bcr|%C0bclr} %t0,%j0"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (pc)
|
||||
@ -8620,7 +8678,8 @@
|
||||
(return)))]
|
||||
"direct_return ()"
|
||||
"{%C0bcr|%C0bclr} %T0,%j0"
|
||||
[(set_attr "length" "8")])
|
||||
[(set_attr "type" "branch")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Unconditional branch and return.
|
||||
|
||||
@ -8628,7 +8687,8 @@
|
||||
[(set (pc)
|
||||
(label_ref (match_operand 0 "" "")))]
|
||||
""
|
||||
"b %l0")
|
||||
"b %l0"
|
||||
[(set_attr "type" "branch")])
|
||||
|
||||
(define_insn "return"
|
||||
[(return)]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user