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aarch-common-protos.h (struct mem_cost_table): Added new fields loadv and storev.
gcc/ChangeLog: 2015-05-20 Kugan Vivekanandarajah <kuganv@linaro.org> Jim Wilson <jim.wilson@linaro.org> * config/arm/aarch-common-protos.h (struct mem_cost_table): Added new fields loadv and storev. * config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs): Initialize loadv and storev. * config/arm/aarch-cost-tables.h (generic_extra_costs): Likewise. (cortexa53_extra_costs): Likewise. (cortexa57_extra_costs): Likewise. (xgene1_extra_costs): Likewise. * config/aarch64/aarch64.c (aarch64_rtx_costs): Update vector rtx_costs. 2015-05-20 Kugan Vivekanandarajah <kuganv@linaro.org> * config/arm/arm.c (cortexa9_extra_costs): Initialize loadv and storev. (cortexa8_extra_costs): Likewise. (cortexa5_extra_costs): Likewise. (cortexa7_extra_costs): Likewise. (cortexa12_extra_costs): Likewise. (cortexa15_extra_costs): Likewise. (v7m_extra_costs): Likewise. Co-Authored-By: Jim Wilson <jim.wilson@linaro.org> From-SVN: r223432
This commit is contained in:
Kugan Vivekanandarajah
Kugan Vivekanandarajah
parent
c725e7f87b
commit
b6875aac2b
@ -1,3 +1,28 @@
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2015-05-20 Kugan Vivekanandarajah <kuganv@linaro.org>
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Jim Wilson <jim.wilson@linaro.org>
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* config/arm/aarch-common-protos.h (struct mem_cost_table): Added
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new fields loadv and storev.
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* config/aarch64/aarch64-cost-tables.h (thunderx_extra_costs):
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Initialize loadv and storev.
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* config/arm/aarch-cost-tables.h (generic_extra_costs): Likewise.
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(cortexa53_extra_costs): Likewise.
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(cortexa57_extra_costs): Likewise.
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(xgene1_extra_costs): Likewise.
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* config/aarch64/aarch64.c (aarch64_rtx_costs): Update vector
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rtx_costs.
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2015-05-20 Kugan Vivekanandarajah <kuganv@linaro.org>
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* config/arm/arm.c (cortexa9_extra_costs): Initialize loadv and
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storev.
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(cortexa8_extra_costs): Likewise.
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(cortexa5_extra_costs): Likewise.
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(cortexa7_extra_costs): Likewise.
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(cortexa12_extra_costs): Likewise.
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(cortexa15_extra_costs): Likewise.
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(v7m_extra_costs): Likewise.
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2015-05-20 Jeff Law <law@redhat.com>
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* tree-ssa-threadupdate.c (thread_single_edge): Use delete_jump_thread
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@ -83,7 +83,9 @@ const struct cpu_cost_table thunderx_extra_costs =
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0, /* N/A: Stm_regs_per_insn_subsequent. */
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0, /* Storef. */
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0, /* Stored. */
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COSTS_N_INSNS (1) /* Store_unaligned. */
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COSTS_N_INSNS (1), /* Store_unaligned. */
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COSTS_N_INSNS (1), /* Loadv. */
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COSTS_N_INSNS (1) /* Storev. */
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},
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{
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/* FP SFmode */
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@ -5617,16 +5617,6 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
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above this default. */
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*cost = COSTS_N_INSNS (1);
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/* TODO: The cost infrastructure currently does not handle
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vector operations. Assume that all vector operations
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are equally expensive. */
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if (VECTOR_MODE_P (mode))
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{
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if (speed)
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*cost += extra_cost->vect.alu;
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return true;
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}
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switch (code)
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{
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case SET:
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@ -5641,7 +5631,9 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
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if (speed)
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{
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rtx address = XEXP (op0, 0);
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if (GET_MODE_CLASS (mode) == MODE_INT)
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->ldst.storev;
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else if (GET_MODE_CLASS (mode) == MODE_INT)
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*cost += extra_cost->ldst.store;
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else if (mode == SFmode)
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*cost += extra_cost->ldst.storef;
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@ -5662,15 +5654,22 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
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/* Fall through. */
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case REG:
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/* The cost is one per vector-register copied. */
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if (VECTOR_MODE_P (GET_MODE (op0)) && REG_P (op1))
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{
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int n_minus_1 = (GET_MODE_SIZE (GET_MODE (op0)) - 1)
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/ GET_MODE_SIZE (V4SImode);
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*cost = COSTS_N_INSNS (n_minus_1 + 1);
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}
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/* const0_rtx is in general free, but we will use an
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instruction to set a register to 0. */
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if (REG_P (op1) || op1 == const0_rtx)
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{
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/* The cost is 1 per register copied. */
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int n_minus_1 = (GET_MODE_SIZE (GET_MODE (op0)) - 1)
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else if (REG_P (op1) || op1 == const0_rtx)
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{
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/* The cost is 1 per register copied. */
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int n_minus_1 = (GET_MODE_SIZE (GET_MODE (op0)) - 1)
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/ UNITS_PER_WORD;
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*cost = COSTS_N_INSNS (n_minus_1 + 1);
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}
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*cost = COSTS_N_INSNS (n_minus_1 + 1);
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}
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else
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/* Cost is just the cost of the RHS of the set. */
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*cost += rtx_cost (op1, SET, 1, speed);
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@ -5768,7 +5767,9 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
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approximation for the additional cost of the addressing
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mode. */
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rtx address = XEXP (x, 0);
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if (GET_MODE_CLASS (mode) == MODE_INT)
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->ldst.loadv;
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else if (GET_MODE_CLASS (mode) == MODE_INT)
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*cost += extra_cost->ldst.load;
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else if (mode == SFmode)
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*cost += extra_cost->ldst.loadf;
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@ -5785,6 +5786,16 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
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case NEG:
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op0 = XEXP (x, 0);
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if (VECTOR_MODE_P (mode))
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{
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if (speed)
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{
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/* FNEG. */
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*cost += extra_cost->vect.alu;
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}
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return false;
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}
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if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
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{
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if (GET_RTX_CLASS (GET_CODE (op0)) == RTX_COMPARE
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@ -5823,7 +5834,12 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
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case CLRSB:
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case CLZ:
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if (speed)
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*cost += extra_cost->alu.clz;
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{
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else
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*cost += extra_cost->alu.clz;
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}
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return false;
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@ -5909,6 +5925,20 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
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return false;
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}
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if (VECTOR_MODE_P (mode))
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{
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/* Vector compare. */
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if (speed)
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*cost += extra_cost->vect.alu;
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if (aarch64_float_const_zero_rtx_p (op1))
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{
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/* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
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cost. */
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return true;
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}
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return false;
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}
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return false;
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case MINUS:
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@ -5961,12 +5991,21 @@ cost_minus:
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if (speed)
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{
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if (GET_MODE_CLASS (mode) == MODE_INT)
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/* SUB(S). */
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*cost += extra_cost->alu.arith;
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if (VECTOR_MODE_P (mode))
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{
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/* Vector SUB. */
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*cost += extra_cost->vect.alu;
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}
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else if (GET_MODE_CLASS (mode) == MODE_INT)
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{
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/* SUB(S). */
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*cost += extra_cost->alu.arith;
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}
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else if (GET_MODE_CLASS (mode) == MODE_FLOAT)
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/* FSUB. */
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*cost += extra_cost->fp[mode == DFmode].addsub;
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{
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/* FSUB. */
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*cost += extra_cost->fp[mode == DFmode].addsub;
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}
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}
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return true;
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}
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@ -6030,12 +6069,21 @@ cost_plus:
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if (speed)
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{
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if (GET_MODE_CLASS (mode) == MODE_INT)
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/* ADD. */
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*cost += extra_cost->alu.arith;
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if (VECTOR_MODE_P (mode))
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{
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/* Vector ADD. */
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*cost += extra_cost->vect.alu;
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}
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else if (GET_MODE_CLASS (mode) == MODE_INT)
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{
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/* ADD. */
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*cost += extra_cost->alu.arith;
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}
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else if (GET_MODE_CLASS (mode) == MODE_FLOAT)
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/* FADD. */
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*cost += extra_cost->fp[mode == DFmode].addsub;
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{
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/* FADD. */
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*cost += extra_cost->fp[mode == DFmode].addsub;
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}
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}
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return true;
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}
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@ -6044,8 +6092,12 @@ cost_plus:
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*cost = COSTS_N_INSNS (1);
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if (speed)
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*cost += extra_cost->alu.rev;
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{
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else
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*cost += extra_cost->alu.rev;
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}
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return false;
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case IOR:
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@ -6053,10 +6105,14 @@ cost_plus:
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{
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*cost = COSTS_N_INSNS (1);
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if (speed)
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*cost += extra_cost->alu.rev;
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return true;
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if (speed)
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{
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else
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*cost += extra_cost->alu.rev;
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}
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return true;
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}
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if (aarch64_extr_rtx_p (x, &op0, &op1))
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@ -6075,6 +6131,13 @@ cost_plus:
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op0 = XEXP (x, 0);
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op1 = XEXP (x, 1);
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if (VECTOR_MODE_P (mode))
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{
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if (speed)
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*cost += extra_cost->vect.alu;
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return true;
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}
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if (code == AND
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&& GET_CODE (op0) == MULT
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&& CONST_INT_P (XEXP (op0, 1))
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@ -6143,6 +6206,13 @@ cost_plus:
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x = XEXP (x, 0);
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op0 = aarch64_strip_shift (x);
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if (VECTOR_MODE_P (mode))
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{
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/* Vector NOT. */
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*cost += extra_cost->vect.alu;
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return false;
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}
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/* MVN-shifted-reg. */
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if (op0 != x)
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{
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@ -6214,10 +6284,19 @@ cost_plus:
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return true;
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}
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/* UXTB/UXTH. */
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if (speed)
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*cost += extra_cost->alu.extend;
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{
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if (VECTOR_MODE_P (mode))
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{
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/* UMOV. */
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*cost += extra_cost->vect.alu;
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}
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else
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{
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/* UXTB/UXTH. */
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*cost += extra_cost->alu.extend;
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}
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}
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return false;
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case SIGN_EXTEND:
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@ -6237,7 +6316,12 @@ cost_plus:
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}
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if (speed)
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*cost += extra_cost->alu.extend;
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{
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else
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*cost += extra_cost->alu.extend;
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}
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return false;
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case ASHIFT:
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@ -6246,10 +6330,20 @@ cost_plus:
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if (CONST_INT_P (op1))
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{
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/* LSL (immediate), UBMF, UBFIZ and friends. These are all
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aliases. */
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if (speed)
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*cost += extra_cost->alu.shift;
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{
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if (VECTOR_MODE_P (mode))
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{
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/* Vector shift (immediate). */
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*cost += extra_cost->vect.alu;
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}
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else
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{
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/* LSL (immediate), UBMF, UBFIZ and friends. These are all
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aliases. */
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*cost += extra_cost->alu.shift;
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}
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}
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/* We can incorporate zero/sign extend for free. */
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if (GET_CODE (op0) == ZERO_EXTEND
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@ -6261,10 +6355,19 @@ cost_plus:
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}
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else
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{
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/* LSLV. */
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if (speed)
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*cost += extra_cost->alu.shift_reg;
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{
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if (VECTOR_MODE_P (mode))
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{
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/* Vector shift (register). */
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*cost += extra_cost->vect.alu;
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}
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else
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{
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/* LSLV. */
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*cost += extra_cost->alu.shift_reg;
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}
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}
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return false; /* All arguments need to be in registers. */
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}
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@ -6279,7 +6382,12 @@ cost_plus:
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{
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/* ASR (immediate) and friends. */
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if (speed)
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*cost += extra_cost->alu.shift;
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{
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else
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*cost += extra_cost->alu.shift;
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}
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*cost += rtx_cost (op0, (enum rtx_code) code, 0, speed);
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return true;
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@ -6289,8 +6397,12 @@ cost_plus:
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/* ASR (register) and friends. */
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if (speed)
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*cost += extra_cost->alu.shift_reg;
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{
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else
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*cost += extra_cost->alu.shift_reg;
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}
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return false; /* All arguments need to be in registers. */
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}
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@ -6338,7 +6450,12 @@ cost_plus:
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case SIGN_EXTRACT:
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/* UBFX/SBFX. */
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if (speed)
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*cost += extra_cost->alu.bfx;
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{
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else
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*cost += extra_cost->alu.bfx;
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}
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/* We can trust that the immediates used will be correct (there
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are no by-register forms), so we need only cost op0. */
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@ -6355,7 +6472,9 @@ cost_plus:
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case UMOD:
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if (speed)
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{
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if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
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*cost += (extra_cost->mult[GET_MODE (x) == DImode].add
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+ extra_cost->mult[GET_MODE (x) == DImode].idiv);
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else if (GET_MODE (x) == DFmode)
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@ -6372,7 +6491,9 @@ cost_plus:
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case SQRT:
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if (speed)
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{
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if (GET_MODE_CLASS (mode) == MODE_INT)
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else if (GET_MODE_CLASS (mode) == MODE_INT)
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/* There is no integer SQRT, so only DIV and UDIV can get
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here. */
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*cost += extra_cost->mult[mode == DImode].idiv;
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@ -6404,7 +6525,12 @@ cost_plus:
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op2 = XEXP (x, 2);
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if (speed)
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*cost += extra_cost->fp[mode == DFmode].fma;
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{
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if (VECTOR_MODE_P (mode))
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*cost += extra_cost->vect.alu;
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else
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*cost += extra_cost->fp[mode == DFmode].fma;
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}
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/* FMSUB, FNMADD, and FNMSUB are free. */
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if (GET_CODE (op0) == NEG)
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@ -6450,12 +6576,28 @@ cost_plus:
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case FLOAT_EXTEND:
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if (speed)
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*cost += extra_cost->fp[mode == DFmode].widen;
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{
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if (VECTOR_MODE_P (mode))
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{
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/*Vector truncate. */
|
||||
*cost += extra_cost->vect.alu;
|
||||
}
|
||||
else
|
||||
*cost += extra_cost->fp[mode == DFmode].widen;
|
||||
}
|
||||
return false;
|
||||
|
||||
case FLOAT_TRUNCATE:
|
||||
if (speed)
|
||||
*cost += extra_cost->fp[mode == DFmode].narrow;
|
||||
{
|
||||
if (VECTOR_MODE_P (mode))
|
||||
{
|
||||
/*Vector conversion. */
|
||||
*cost += extra_cost->vect.alu;
|
||||
}
|
||||
else
|
||||
*cost += extra_cost->fp[mode == DFmode].narrow;
|
||||
}
|
||||
return false;
|
||||
|
||||
case FIX:
|
||||
@ -6476,13 +6618,23 @@ cost_plus:
|
||||
}
|
||||
|
||||
if (speed)
|
||||
*cost += extra_cost->fp[GET_MODE (x) == DFmode].toint;
|
||||
|
||||
{
|
||||
if (VECTOR_MODE_P (mode))
|
||||
*cost += extra_cost->vect.alu;
|
||||
else
|
||||
*cost += extra_cost->fp[GET_MODE (x) == DFmode].toint;
|
||||
}
|
||||
*cost += rtx_cost (x, (enum rtx_code) code, 0, speed);
|
||||
return true;
|
||||
|
||||
case ABS:
|
||||
if (GET_MODE_CLASS (mode) == MODE_FLOAT)
|
||||
if (VECTOR_MODE_P (mode))
|
||||
{
|
||||
/* ABS (vector). */
|
||||
if (speed)
|
||||
*cost += extra_cost->vect.alu;
|
||||
}
|
||||
else if (GET_MODE_CLASS (mode) == MODE_FLOAT)
|
||||
{
|
||||
op0 = XEXP (x, 0);
|
||||
|
||||
@ -6515,10 +6667,15 @@ cost_plus:
|
||||
case SMIN:
|
||||
if (speed)
|
||||
{
|
||||
/* FMAXNM/FMINNM/FMAX/FMIN.
|
||||
TODO: This may not be accurate for all implementations, but
|
||||
we do not model this in the cost tables. */
|
||||
*cost += extra_cost->fp[mode == DFmode].addsub;
|
||||
if (VECTOR_MODE_P (mode))
|
||||
*cost += extra_cost->vect.alu;
|
||||
else
|
||||
{
|
||||
/* FMAXNM/FMINNM/FMAX/FMIN.
|
||||
TODO: This may not be accurate for all implementations, but
|
||||
we do not model this in the cost tables. */
|
||||
*cost += extra_cost->fp[mode == DFmode].addsub;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
|
||||
|
||||
@ -102,6 +102,8 @@ struct mem_cost_table
|
||||
const int storef; /* SFmode. */
|
||||
const int stored; /* DFmode. */
|
||||
const int store_unaligned; /* Extra for unaligned stores. */
|
||||
const int loadv; /* Vector load. */
|
||||
const int storev; /* Vector store. */
|
||||
};
|
||||
|
||||
struct fp_cost_table
|
||||
|
||||
@ -81,7 +81,9 @@ const struct cpu_cost_table generic_extra_costs =
|
||||
1, /* stm_regs_per_insn_subsequent. */
|
||||
COSTS_N_INSNS (2), /* storef. */
|
||||
COSTS_N_INSNS (3), /* stored. */
|
||||
COSTS_N_INSNS (1) /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
@ -182,7 +184,9 @@ const struct cpu_cost_table cortexa53_extra_costs =
|
||||
2, /* stm_regs_per_insn_subsequent. */
|
||||
0, /* storef. */
|
||||
0, /* stored. */
|
||||
COSTS_N_INSNS (1) /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
@ -283,7 +287,9 @@ const struct cpu_cost_table cortexa57_extra_costs =
|
||||
2, /* stm_regs_per_insn_subsequent. */
|
||||
0, /* storef. */
|
||||
0, /* stored. */
|
||||
COSTS_N_INSNS (1) /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
@ -385,6 +391,8 @@ const struct cpu_cost_table xgene1_extra_costs =
|
||||
0, /* storef. */
|
||||
0, /* stored. */
|
||||
0, /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
|
||||
@ -1024,7 +1024,9 @@ const struct cpu_cost_table cortexa9_extra_costs =
|
||||
2, /* stm_regs_per_insn_subsequent. */
|
||||
COSTS_N_INSNS (1), /* storef. */
|
||||
COSTS_N_INSNS (1), /* stored. */
|
||||
COSTS_N_INSNS (1) /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
@ -1125,7 +1127,9 @@ const struct cpu_cost_table cortexa8_extra_costs =
|
||||
2, /* stm_regs_per_insn_subsequent. */
|
||||
COSTS_N_INSNS (1), /* storef. */
|
||||
COSTS_N_INSNS (1), /* stored. */
|
||||
COSTS_N_INSNS (1) /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
@ -1227,7 +1231,9 @@ const struct cpu_cost_table cortexa5_extra_costs =
|
||||
2, /* stm_regs_per_insn_subsequent. */
|
||||
COSTS_N_INSNS (2), /* storef. */
|
||||
COSTS_N_INSNS (2), /* stored. */
|
||||
COSTS_N_INSNS (1) /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
@ -1330,7 +1336,9 @@ const struct cpu_cost_table cortexa7_extra_costs =
|
||||
2, /* stm_regs_per_insn_subsequent. */
|
||||
COSTS_N_INSNS (2), /* storef. */
|
||||
COSTS_N_INSNS (2), /* stored. */
|
||||
COSTS_N_INSNS (1) /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
@ -1431,7 +1439,9 @@ const struct cpu_cost_table cortexa12_extra_costs =
|
||||
2, /* stm_regs_per_insn_subsequent. */
|
||||
COSTS_N_INSNS (2), /* storef. */
|
||||
COSTS_N_INSNS (2), /* stored. */
|
||||
0 /* store_unaligned. */
|
||||
0, /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
@ -1532,7 +1542,9 @@ const struct cpu_cost_table cortexa15_extra_costs =
|
||||
2, /* stm_regs_per_insn_subsequent. */
|
||||
0, /* storef. */
|
||||
0, /* stored. */
|
||||
0 /* store_unaligned. */
|
||||
0, /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
@ -1633,7 +1645,9 @@ const struct cpu_cost_table v7m_extra_costs =
|
||||
1, /* stm_regs_per_insn_subsequent. */
|
||||
COSTS_N_INSNS (2), /* storef. */
|
||||
COSTS_N_INSNS (3), /* stored. */
|
||||
COSTS_N_INSNS (1) /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* store_unaligned. */
|
||||
COSTS_N_INSNS (1), /* loadv. */
|
||||
COSTS_N_INSNS (1) /* storev. */
|
||||
},
|
||||
{
|
||||
/* FP SFmode */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user