diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e32ce399e739..ed17a6b5b0dd 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,35 @@ +2004-11-06 Ulrich Weigand + + * config/s390/s390.md (attribute "op_type"): Default to "NN". + (attribute "atype"): Default to "agen". + (attribute "length"): Default to 6. + (define_asm_attibutes): Remove. + ("movti", "*movdi_64", "*movdi_31", "*movsi_zarch", "*movsi_esa", + "*movhi", "*movqi", "*movdf_64", "*movdf_31", "movsf", + "*clc", "*mvc", "*nc", "*oc", "*xc", "*xc_zero"): + Do not set type attribute to "cs" where already default. + ("*cmpint_si", "*cmpint_di", "fix_truncdfsi2_ibm", "floatsidf2_ibm", + "*negdi2_31"): + Do not set type attribute to "other" where already default. + ("movti", "*movdi_64", "*movdi_31", "*movdf_31", + "*strlendi", "*strlensi", + "*movmem_long_64", "*movmem_long_31", + "*clrmem_long_64", "*clrmem_long_31", + "*cmpmem_long_64", "*cmpmem_long_31", + "*cmpint_si", "*cmpint_di", + "addti3", "*adddi3_31z", "*adddi3_31", + "subti3", "*subdi3_31z", "*subdi3_31", "*negdi2_31", + "*sconddi", "*scondsi", "*sconddi_neg", "*scondsi_neg", + "fix_truncdfsi2_ibm", "floatsidf2_ibm", "extendsfdf2_ibm", + "*pool_entry", "pool_align", "pool_section_start", + "pool_section_end", "main_pool", "reload_base_31", "pool"): + Do not set op_type attribute to "NN" where already default. + ("*extractqi", "*extracthi", "*zero_extendhisi2_31", + "*zero_extendqisi2_31", "*zero_extendqihi2_31", + "fix_truncdfsi2_ibm", "floatsidf2_ibm"): + Do not set atype attribute to "agen" where already default. + ("*movmem_short", "*clrmem_short", "*cmpmem_short"): Don't set op_type. + 2004-11-06 Richard Sandiford * config/mips/t-iris6 (tp-bit.c): Fix target filename. diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index ed19615514b5..744485964c36 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -148,7 +148,7 @@ (define_attr "op_type" "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" - (const_string "RX")) + (const_string "NN")) ;; Instruction type attribute used for scheduling. @@ -168,7 +168,7 @@ ;; reg: Instruction does not use the agen unit (define_attr "atype" "agen,reg" -(cond [ (eq_attr "op_type" "E") (const_string "reg") + (cond [(eq_attr "op_type" "E") (const_string "reg") (eq_attr "op_type" "RR") (const_string "reg") (eq_attr "op_type" "RX") (const_string "agen") (eq_attr "op_type" "RI") (const_string "reg") @@ -185,12 +185,12 @@ (eq_attr "op_type" "RXY") (const_string "agen") (eq_attr "op_type" "RSY") (const_string "agen") (eq_attr "op_type" "SIY") (const_string "agen")] - (const_string "reg"))) + (const_string "agen"))) ;; Length in bytes. (define_attr "length" "" -(cond [ (eq_attr "op_type" "E") (const_int 2) + (cond [(eq_attr "op_type" "E") (const_int 2) (eq_attr "op_type" "RR") (const_int 2) (eq_attr "op_type" "RX") (const_int 4) (eq_attr "op_type" "RI") (const_int 4) @@ -207,12 +207,7 @@ (eq_attr "op_type" "RXY") (const_int 6) (eq_attr "op_type" "RSY") (const_int 6) (eq_attr "op_type" "SIY") (const_int 6)] - (const_int 4))) - -;; Define attributes for `asm' insns. - -(define_asm_attributes [(set_attr "type" "other") - (set_attr "op_type" "NN")]) + (const_int 6))) ;; Processor type. This attribute must exactly match the processor_type @@ -681,8 +676,7 @@ "s390_match_ccmode (insn, CCUmode) && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "clc\t%O0(%2,%R0),%S1" - [(set_attr "op_type" "SS") - (set_attr "type" "cs")]) + [(set_attr "op_type" "SS")]) (define_split [(set (reg 33) @@ -810,8 +804,8 @@ # # #" - [(set_attr "op_type" "RSY,RSY,NN,NN,SS") - (set_attr "type" "lm,stm,*,*,cs")]) + [(set_attr "op_type" "RSY,RSY,*,*,SS") + (set_attr "type" "lm,stm,*,*,*")]) (define_split [(set (match_operand:TI 0 "nonimmediate_operand" "") @@ -914,9 +908,10 @@ stam\t%1,%N1,%S0 lam\t%0,%N0,%S1 #" - [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,NN,NN,RS,RS,SS") - (set_attr "type" "*,*,*,*,*,la,lr,load,store,floadd,floadd,floadd, - fstored,fstored,*,*,*,*,cs")]) + [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, + RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") + (set_attr "type" "*,*,*,*,*,la,lr,load,store, + floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -966,8 +961,8 @@ std\t%1,%0 stdy\t%1,%0 #" - [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS") - (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")]) + [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS") + (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")]) (define_split [(set (match_operand:DI 0 "nonimmediate_operand" "") @@ -1127,8 +1122,10 @@ stam\t%1,%1,%S0 lam\t%0,%0,%S1 #" - [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") - (set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,*,*,*,*,cs")]) + [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY, + RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") + (set_attr "type" "*,*,*,la,lr,load,load,store,store, + floads,floads,floads,fstores,fstores,*,*,*,*,*")]) (define_insn "*movsi_esa" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") @@ -1148,7 +1145,7 @@ lam\t%0,%0,%S1 #" [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") - (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,cs")]) + (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")]) (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -1276,7 +1273,7 @@ sthy\t%1,%0 #" [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") - (set_attr "type" "lr,*,*,*,store,store,cs")]) + (set_attr "type" "lr,*,*,*,store,store,*")]) (define_peephole2 [(set (match_operand:HI 0 "register_operand" "") @@ -1325,7 +1322,7 @@ mviy\t%S0,%b1 #" [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") - (set_attr "type" "lr,*,*,*,store,store,store,store,cs")]) + (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) (define_peephole2 [(set (match_operand:QI 0 "nonimmediate_operand" "") @@ -1405,7 +1402,7 @@ stg\t%1,%0 #" [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") - (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")]) + (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")]) (define_insn "*movdf_31" [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") @@ -1422,8 +1419,8 @@ # # #" - [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS") - (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")]) + [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS") + (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")]) (define_split [(set (match_operand:DF 0 "nonimmediate_operand" "") @@ -1499,7 +1496,8 @@ sty\t%1,%0 #" [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") - (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")]) + (set_attr "type" "floads,floads,floads,fstores,fstores, + lr,load,load,store,store,*")]) ; ; movcc instruction pattern @@ -1530,8 +1528,7 @@ (use (match_operand 2 "const_int_operand" "n"))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "mvc\t%O0(%2,%R0),%S1" - [(set_attr "op_type" "SS") - (set_attr "type" "cs")]) + [(set_attr "op_type" "SS")]) (define_split [(set (match_operand 0 "memory_operand" "") @@ -1804,9 +1801,8 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "srst\t%0,%1\;jo\t.-4" - [(set_attr "op_type" "NN") - (set_attr "type" "vs") - (set_attr "length" "8")]) + [(set_attr "length" "8") + (set_attr "type" "vs")]) (define_expand "strlensi" [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) @@ -1840,9 +1836,8 @@ (clobber (reg:CC 33))] "!TARGET_64BIT" "srst\t%0,%1\;jo\t.-4" - [(set_attr "op_type" "NN") - (set_attr "type" "vs") - (set_attr "length" "8")]) + [(set_attr "length" "8") + (set_attr "type" "vs")]) ; ; movmemM instruction pattern(s). @@ -1886,8 +1881,7 @@ "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) && GET_MODE (operands[4]) == Pmode" "#" - [(set_attr "op_type" "SS,RX,RX") - (set_attr "type" "cs")]) + [(set_attr "type" "cs")]) (define_split [(set (match_operand:BLK 0 "memory_operand" "") @@ -1975,9 +1969,8 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "mvcle\t%0,%1,0\;jo\t.-4" - [(set_attr "op_type" "NN") - (set_attr "type" "vs") - (set_attr "length" "8")]) + [(set_attr "length" "8") + (set_attr "type" "vs")]) (define_insn "*movmem_long_31" [(clobber (match_operand:DI 0 "register_operand" "=d")) @@ -1989,9 +1982,8 @@ (clobber (reg:CC 33))] "!TARGET_64BIT" "mvcle\t%0,%1,0\;jo\t.-4" - [(set_attr "op_type" "NN") - (set_attr "type" "vs") - (set_attr "length" "8")]) + [(set_attr "length" "8") + (set_attr "type" "vs")]) ; ; clrmemM instruction pattern(s). @@ -2037,8 +2029,7 @@ "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) && GET_MODE (operands[3]) == Pmode" "#" - [(set_attr "op_type" "SS,RX,RX") - (set_attr "type" "cs")]) + [(set_attr "type" "cs")]) (define_split [(set (match_operand:BLK 0 "memory_operand" "") @@ -2125,9 +2116,8 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "mvcle\t%0,%1,0\;jo\t.-4" - [(set_attr "op_type" "NN") - (set_attr "type" "vs") - (set_attr "length" "8")]) + [(set_attr "length" "8") + (set_attr "type" "vs")]) (define_insn "*clrmem_long_31" [(clobber (match_operand:DI 0 "register_operand" "=d")) @@ -2138,9 +2128,8 @@ (clobber (reg:CC 33))] "!TARGET_64BIT" "mvcle\t%0,%1,0\;jo\t.-4" - [(set_attr "op_type" "NN") - (set_attr "type" "vs") - (set_attr "length" "8")]) + [(set_attr "length" "8") + (set_attr "type" "vs")]) ; ; cmpmemM instruction pattern(s). @@ -2180,8 +2169,7 @@ "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) && GET_MODE (operands[4]) == Pmode" "#" - [(set_attr "op_type" "SS,RX,RX") - (set_attr "type" "cs")]) + [(set_attr "type" "cs")]) (define_split [(set (reg:CCU 33) @@ -2272,9 +2260,8 @@ (use (match_dup 3))] "TARGET_64BIT" "clcle\t%0,%1,0\;jo\t.-4" - [(set_attr "op_type" "NN") - (set_attr "type" "vs") - (set_attr "length" "8")]) + [(set_attr "length" "8") + (set_attr "type" "vs")]) (define_insn "*cmpmem_long_31" [(clobber (match_operand:DI 0 "register_operand" "=d")) @@ -2286,9 +2273,8 @@ (use (match_dup 3))] "!TARGET_64BIT" "clcle\t%0,%1,0\;jo\t.-4" - [(set_attr "op_type" "NN") - (set_attr "type" "vs") - (set_attr "length" "8")]) + [(set_attr "length" "8") + (set_attr "type" "vs")]) ; Convert condition code to integer in range (-1, 0, 1) @@ -2303,9 +2289,7 @@ output_asm_insn ("sr\t%0,%0", operands); return "lcr\t%0,%0"; } - [(set_attr "op_type" "NN") - (set_attr "length" "16") - (set_attr "type" "other")]) + [(set_attr "length" "16")]) (define_insn "*cmpint_di" [(set (match_operand:DI 0 "register_operand" "=d") @@ -2318,9 +2302,7 @@ output_asm_insn ("sgr\t%0,%0", operands); return "lcgr\t%0,%0"; } - [(set_attr "op_type" "NN") - (set_attr "length" "20") - (set_attr "type" "other")]) + [(set_attr "length" "20")]) ;; @@ -2382,8 +2364,7 @@ { operands[2] = GEN_INT (32 - INTVAL (operands[2])); operands[1] = change_address (operands[1], QImode, 0); -} - [(set_attr "atype" "agen")]) +}) (define_insn_and_split "*extracthi" [(set (match_operand:SI 0 "register_operand" "=d") @@ -2402,8 +2383,7 @@ { operands[2] = GEN_INT (32 - INTVAL (operands[2])); operands[1] = change_address (operands[1], HImode, 0); -} - [(set_attr "atype" "agen")]) +}) ; ; extendsidi2 instruction pattern(s). @@ -2786,8 +2766,7 @@ (parallel [(set (strict_low_part (match_dup 2)) (match_dup 1)) (clobber (reg:CC 33))])] - "operands[2] = gen_lowpart (HImode, operands[0]);" - [(set_attr "atype" "agen")]) + "operands[2] = gen_lowpart (HImode, operands[0]);") ; ; zero_extendqisi2 instruction pattern(s). @@ -2820,8 +2799,7 @@ "&& reload_completed" [(set (match_dup 0) (const_int 0)) (set (strict_low_part (match_dup 2)) (match_dup 1))] - "operands[2] = gen_lowpart (QImode, operands[0]);" - [(set_attr "atype" "agen")]) + "operands[2] = gen_lowpart (QImode, operands[0]);") ; ; zero_extendqihi2 instruction pattern(s). @@ -2854,8 +2832,7 @@ "&& reload_completed" [(set (match_dup 0) (const_int 0)) (set (strict_low_part (match_dup 2)) (match_dup 1))] - "operands[2] = gen_lowpart (QImode, operands[0]);" - [(set_attr "atype" "agen")]) + "operands[2] = gen_lowpart (QImode, operands[0]);") ; @@ -2989,10 +2966,7 @@ output_asm_insn ("xi\t%N4,128", operands); return "l\t%0,%N4"; } - [(set_attr "op_type" "NN") - (set_attr "type" "other") - (set_attr "atype" "agen") - (set_attr "length" "20")]) + [(set_attr "length" "20")]) ; ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). @@ -3173,10 +3147,7 @@ output_asm_insn ("ld\t%0,%3", operands); return "sd\t%0,%2"; } - [(set_attr "op_type" "NN") - (set_attr "type" "other" ) - (set_attr "atype" "agen") - (set_attr "length" "20")]) + [(set_attr "length" "20")]) ; ; floatsisf2 instruction pattern(s). @@ -3266,8 +3237,7 @@ "@ sdr\t%0,%0\;ler\t%0,%1 sdr\t%0,%0\;le\t%0,%1" - [(set_attr "op_type" "NN,NN") - (set_attr "length" "4,6") + [(set_attr "length" "4,6") (set_attr "type" "floads,floads")]) @@ -3308,8 +3278,7 @@ operands[5] = operand_subword (operands[2], 0, 0, TImode); operands[6] = operand_subword (operands[0], 1, 0, TImode); operands[7] = operand_subword (operands[1], 1, 0, TImode); - operands[8] = operand_subword (operands[2], 1, 0, TImode);" - [(set_attr "op_type" "NN")]) + operands[8] = operand_subword (operands[2], 1, 0, TImode);") ; ; adddi3 instruction pattern(s). @@ -3495,8 +3464,7 @@ operands[5] = operand_subword (operands[2], 0, 0, DImode); operands[6] = operand_subword (operands[0], 1, 0, DImode); operands[7] = operand_subword (operands[1], 1, 0, DImode); - operands[8] = operand_subword (operands[2], 1, 0, DImode);" - [(set_attr "op_type" "NN")]) + operands[8] = operand_subword (operands[2], 1, 0, DImode);") (define_insn_and_split "*adddi3_31" [(set (match_operand:DI 0 "register_operand" "=&d") @@ -3528,8 +3496,7 @@ operands[6] = operand_subword (operands[0], 1, 0, DImode); operands[7] = operand_subword (operands[1], 1, 0, DImode); operands[8] = operand_subword (operands[2], 1, 0, DImode); - operands[9] = gen_label_rtx ();" - [(set_attr "op_type" "NN")]) + operands[9] = gen_label_rtx ();") (define_expand "adddi3" [(parallel @@ -3832,8 +3799,7 @@ operands[5] = operand_subword (operands[2], 0, 0, TImode); operands[6] = operand_subword (operands[0], 1, 0, TImode); operands[7] = operand_subword (operands[1], 1, 0, TImode); - operands[8] = operand_subword (operands[2], 1, 0, TImode);" - [(set_attr "op_type" "NN")]) + operands[8] = operand_subword (operands[2], 1, 0, TImode);") ; ; subdi3 instruction pattern(s). @@ -3992,8 +3958,7 @@ operands[5] = operand_subword (operands[2], 0, 0, DImode); operands[6] = operand_subword (operands[0], 1, 0, DImode); operands[7] = operand_subword (operands[1], 1, 0, DImode); - operands[8] = operand_subword (operands[2], 1, 0, DImode);" - [(set_attr "op_type" "NN")]) + operands[8] = operand_subword (operands[2], 1, 0, DImode);") (define_insn_and_split "*subdi3_31" [(set (match_operand:DI 0 "register_operand" "=&d") @@ -4025,8 +3990,7 @@ operands[6] = operand_subword (operands[0], 1, 0, DImode); operands[7] = operand_subword (operands[1], 1, 0, DImode); operands[8] = operand_subword (operands[2], 1, 0, DImode); - operands[9] = gen_label_rtx ();" - [(set_attr "op_type" "NN")]) + operands[9] = gen_label_rtx ();") (define_expand "subdi3" [(parallel @@ -4431,8 +4395,7 @@ [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0)) (match_dup 1))) (clobber (reg:CC 33))])] - "" - [(set_attr "op_type" "NN")]) + "") (define_insn_and_split "*scondsi" [(set (match_operand:SI 0 "register_operand" "=&d") @@ -4446,8 +4409,7 @@ [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0)) (match_dup 1))) (clobber (reg:CC 33))])] - "" - [(set_attr "op_type" "NN")]) + "") (define_insn_and_split "*sconddi_neg" [(set (match_operand:DI 0 "register_operand" "=&d") @@ -4464,8 +4426,7 @@ (parallel [(set (match_dup 0) (neg:DI (match_dup 0))) (clobber (reg:CC 33))])] - "" - [(set_attr "op_type" "NN")]) + "") (define_insn_and_split "*scondsi_neg" [(set (match_operand:SI 0 "register_operand" "=&d") @@ -4482,8 +4443,7 @@ (parallel [(set (match_dup 0) (neg:SI (match_dup 0))) (clobber (reg:CC 33))])] - "" - [(set_attr "op_type" "NN")]) + "") (define_expand "sltu" [(match_operand:SI 0 "register_operand" "")] @@ -5473,8 +5433,7 @@ (clobber (reg:CC 33))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "nc\t%O0(%2,%R0),%S1" - [(set_attr "op_type" "SS") - (set_attr "type" "cs")]) + [(set_attr "op_type" "SS")]) (define_split [(set (match_operand 0 "memory_operand" "") @@ -5763,8 +5722,7 @@ (clobber (reg:CC 33))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "oc\t%O0(%2,%R0),%S1" - [(set_attr "op_type" "SS") - (set_attr "type" "cs")]) + [(set_attr "op_type" "SS")]) (define_split [(set (match_operand 0 "memory_operand" "") @@ -6007,8 +5965,7 @@ (clobber (reg:CC 33))] "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" "xc\t%O0(%2,%R0),%S1" - [(set_attr "op_type" "SS") - (set_attr "type" "cs")]) + [(set_attr "op_type" "SS")]) (define_split [(set (match_operand 0 "memory_operand" "") @@ -6063,8 +6020,7 @@ (clobber (reg:CC 33))] "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" "xc\t%O0(%1,%R0),%S0" - [(set_attr "op_type" "SS") - (set_attr "type" "cs")]) + [(set_attr "op_type" "SS")]) (define_peephole2 [(parallel @@ -6127,9 +6083,7 @@ CODE_LABEL_NUMBER (xop[0])); return ""; } - [(set_attr "op_type" "NN") - (set_attr "type" "other") - (set_attr "length" "10")]) + [(set_attr "length" "10")]) ; ; negsi2 instruction pattern(s). @@ -7721,8 +7675,7 @@ s390_output_pool_entry (operands[0], mode, align); return ""; } - [(set_attr "op_type" "NN") - (set (attr "length") + [(set (attr "length") (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) (define_insn "pool_align" @@ -7730,22 +7683,19 @@ UNSPECV_POOL_ALIGN)] "" ".align\t%0" - [(set_attr "op_type" "NN") - (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) + [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) (define_insn "pool_section_start" [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] "" ".section\t.rodata" - [(set_attr "op_type" "NN") - (set_attr "length" "0")]) + [(set_attr "length" "0")]) (define_insn "pool_section_end" [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] "" ".previous" - [(set_attr "op_type" "NN") - (set_attr "length" "0")]) + [(set_attr "length" "0")]) (define_insn "main_base_31_small" [(set (match_operand 0 "register_operand" "=a") @@ -7776,8 +7726,7 @@ (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] "GET_MODE (operands[0]) == Pmode" "* abort ();" - [(set_attr "op_type" "NN") - (set (attr "type") + [(set (attr "type") (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_string "larl") (const_string "la")))]) @@ -7786,9 +7735,8 @@ (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" "basr\t%0,0\;la\t%0,%1-.(%0)" - [(set_attr "op_type" "NN") - (set_attr "type" "la") - (set_attr "length" "6")]) + [(set_attr "length" "6") + (set_attr "type" "la")]) (define_insn "reload_base_64" [(set (match_operand 0 "register_operand" "=a") @@ -7802,8 +7750,7 @@ [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] "" "* abort ();" - [(set_attr "op_type" "NN") - (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) + [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) ;; ;; Insns related to generating the function prologue and epilogue.