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s390.md (attribute "op_type"): Default to "NN".
* config/s390/s390.md (attribute "op_type"): Default to "NN".
(attribute "atype"): Default to "agen".
(attribute "length"): Default to 6.
(define_asm_attibutes): Remove.
("movti", "*movdi_64", "*movdi_31", "*movsi_zarch", "*movsi_esa",
"*movhi", "*movqi", "*movdf_64", "*movdf_31", "movsf",
"*clc", "*mvc", "*nc", "*oc", "*xc", "*xc_zero"):
Do not set type attribute to "cs" where already default.
("*cmpint_si", "*cmpint_di", "fix_truncdfsi2_ibm", "floatsidf2_ibm",
"*negdi2_31"):
Do not set type attribute to "other" where already default.
("movti", "*movdi_64", "*movdi_31", "*movdf_31",
"*strlendi", "*strlensi",
"*movmem_long_64", "*movmem_long_31",
"*clrmem_long_64", "*clrmem_long_31",
"*cmpmem_long_64", "*cmpmem_long_31",
"*cmpint_si", "*cmpint_di",
"addti3", "*adddi3_31z", "*adddi3_31",
"subti3", "*subdi3_31z", "*subdi3_31", "*negdi2_31",
"*sconddi", "*scondsi", "*sconddi_neg", "*scondsi_neg",
"fix_truncdfsi2_ibm", "floatsidf2_ibm", "extendsfdf2_ibm",
"*pool_entry", "pool_align", "pool_section_start",
"pool_section_end", "main_pool", "reload_base_31", "pool"):
Do not set op_type attribute to "NN" where already default.
("*extractqi", "*extracthi", "*zero_extendhisi2_31",
"*zero_extendqisi2_31", "*zero_extendqihi2_31",
"fix_truncdfsi2_ibm", "floatsidf2_ibm"):
Do not set atype attribute to "agen" where already default.
("*movmem_short", "*clrmem_short", "*cmpmem_short"): Don't set op_type.
From-SVN: r90208
This commit is contained in:
Ulrich Weigand
Ulrich Weigand
parent
9ec0f3c8f5
commit
b628bd8e9d
@ -1,3 +1,35 @@
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2004-11-06 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/s390.md (attribute "op_type"): Default to "NN".
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(attribute "atype"): Default to "agen".
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(attribute "length"): Default to 6.
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(define_asm_attibutes): Remove.
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("movti", "*movdi_64", "*movdi_31", "*movsi_zarch", "*movsi_esa",
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"*movhi", "*movqi", "*movdf_64", "*movdf_31", "movsf",
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"*clc", "*mvc", "*nc", "*oc", "*xc", "*xc_zero"):
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Do not set type attribute to "cs" where already default.
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("*cmpint_si", "*cmpint_di", "fix_truncdfsi2_ibm", "floatsidf2_ibm",
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"*negdi2_31"):
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Do not set type attribute to "other" where already default.
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("movti", "*movdi_64", "*movdi_31", "*movdf_31",
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"*strlendi", "*strlensi",
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"*movmem_long_64", "*movmem_long_31",
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"*clrmem_long_64", "*clrmem_long_31",
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"*cmpmem_long_64", "*cmpmem_long_31",
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"*cmpint_si", "*cmpint_di",
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"addti3", "*adddi3_31z", "*adddi3_31",
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"subti3", "*subdi3_31z", "*subdi3_31", "*negdi2_31",
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"*sconddi", "*scondsi", "*sconddi_neg", "*scondsi_neg",
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"fix_truncdfsi2_ibm", "floatsidf2_ibm", "extendsfdf2_ibm",
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"*pool_entry", "pool_align", "pool_section_start",
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"pool_section_end", "main_pool", "reload_base_31", "pool"):
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Do not set op_type attribute to "NN" where already default.
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("*extractqi", "*extracthi", "*zero_extendhisi2_31",
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"*zero_extendqisi2_31", "*zero_extendqihi2_31",
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"fix_truncdfsi2_ibm", "floatsidf2_ibm"):
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Do not set atype attribute to "agen" where already default.
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("*movmem_short", "*clrmem_short", "*cmpmem_short"): Don't set op_type.
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2004-11-06 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/t-iris6 (tp-bit.c): Fix target filename.
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@ -148,7 +148,7 @@
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(define_attr "op_type"
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"NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
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(const_string "RX"))
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(const_string "NN"))
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;; Instruction type attribute used for scheduling.
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@ -168,7 +168,7 @@
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;; reg: Instruction does not use the agen unit
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(define_attr "atype" "agen,reg"
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(cond [ (eq_attr "op_type" "E") (const_string "reg")
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(cond [(eq_attr "op_type" "E") (const_string "reg")
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(eq_attr "op_type" "RR") (const_string "reg")
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(eq_attr "op_type" "RX") (const_string "agen")
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(eq_attr "op_type" "RI") (const_string "reg")
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@ -185,12 +185,12 @@
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(eq_attr "op_type" "RXY") (const_string "agen")
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(eq_attr "op_type" "RSY") (const_string "agen")
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(eq_attr "op_type" "SIY") (const_string "agen")]
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(const_string "reg")))
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(const_string "agen")))
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;; Length in bytes.
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(define_attr "length" ""
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(cond [ (eq_attr "op_type" "E") (const_int 2)
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(cond [(eq_attr "op_type" "E") (const_int 2)
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(eq_attr "op_type" "RR") (const_int 2)
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(eq_attr "op_type" "RX") (const_int 4)
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(eq_attr "op_type" "RI") (const_int 4)
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@ -207,12 +207,7 @@
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(eq_attr "op_type" "RXY") (const_int 6)
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(eq_attr "op_type" "RSY") (const_int 6)
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(eq_attr "op_type" "SIY") (const_int 6)]
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(const_int 4)))
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;; Define attributes for `asm' insns.
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(define_asm_attributes [(set_attr "type" "other")
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(set_attr "op_type" "NN")])
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(const_int 6)))
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;; Processor type. This attribute must exactly match the processor_type
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@ -681,8 +676,7 @@
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"s390_match_ccmode (insn, CCUmode)
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&& INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
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"clc\t%O0(%2,%R0),%S1"
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[(set_attr "op_type" "SS")
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(set_attr "type" "cs")])
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[(set_attr "op_type" "SS")])
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(define_split
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[(set (reg 33)
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@ -810,8 +804,8 @@
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#
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#
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#"
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[(set_attr "op_type" "RSY,RSY,NN,NN,SS")
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(set_attr "type" "lm,stm,*,*,cs")])
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[(set_attr "op_type" "RSY,RSY,*,*,SS")
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(set_attr "type" "lm,stm,*,*,*")])
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(define_split
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[(set (match_operand:TI 0 "nonimmediate_operand" "")
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@ -914,9 +908,10 @@
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stam\t%1,%N1,%S0
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lam\t%0,%N0,%S1
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#"
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[(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,NN,NN,RS,RS,SS")
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(set_attr "type" "*,*,*,*,*,la,lr,load,store,floadd,floadd,floadd,
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fstored,fstored,*,*,*,*,cs")])
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[(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
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RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
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(set_attr "type" "*,*,*,*,*,la,lr,load,store,
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floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")])
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(define_split
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[(set (match_operand:DI 0 "register_operand" "")
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@ -966,8 +961,8 @@
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std\t%1,%0
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stdy\t%1,%0
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#"
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[(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
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(set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
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[(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
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(set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")])
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(define_split
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[(set (match_operand:DI 0 "nonimmediate_operand" "")
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@ -1127,8 +1122,10 @@
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stam\t%1,%1,%S0
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lam\t%0,%0,%S1
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#"
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[(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
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(set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,*,*,*,*,cs")])
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[(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
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RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
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(set_attr "type" "*,*,*,la,lr,load,load,store,store,
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floads,floads,floads,fstores,fstores,*,*,*,*,*")])
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(define_insn "*movsi_esa"
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[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
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@ -1148,7 +1145,7 @@
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lam\t%0,%0,%S1
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#"
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[(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
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(set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,cs")])
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(set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")])
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(define_peephole2
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[(set (match_operand:SI 0 "register_operand" "")
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@ -1276,7 +1273,7 @@
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sthy\t%1,%0
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#"
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[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
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(set_attr "type" "lr,*,*,*,store,store,cs")])
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(set_attr "type" "lr,*,*,*,store,store,*")])
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(define_peephole2
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[(set (match_operand:HI 0 "register_operand" "")
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@ -1325,7 +1322,7 @@
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mviy\t%S0,%b1
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#"
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[(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
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(set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
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(set_attr "type" "lr,*,*,*,store,store,store,store,*")])
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(define_peephole2
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[(set (match_operand:QI 0 "nonimmediate_operand" "")
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@ -1405,7 +1402,7 @@
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stg\t%1,%0
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#"
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
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(set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
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(set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")])
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(define_insn "*movdf_31"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
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@ -1422,8 +1419,8 @@
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#
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#
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#"
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
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(set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
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(set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")])
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(define_split
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[(set (match_operand:DF 0 "nonimmediate_operand" "")
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@ -1499,7 +1496,8 @@
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sty\t%1,%0
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#"
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
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(set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
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(set_attr "type" "floads,floads,floads,fstores,fstores,
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lr,load,load,store,store,*")])
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;
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; movcc instruction pattern
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@ -1530,8 +1528,7 @@
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(use (match_operand 2 "const_int_operand" "n"))]
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"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
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"mvc\t%O0(%2,%R0),%S1"
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[(set_attr "op_type" "SS")
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(set_attr "type" "cs")])
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[(set_attr "op_type" "SS")])
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(define_split
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[(set (match_operand 0 "memory_operand" "")
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@ -1804,9 +1801,8 @@
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(clobber (reg:CC 33))]
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"TARGET_64BIT"
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"srst\t%0,%1\;jo\t.-4"
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[(set_attr "op_type" "NN")
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(set_attr "type" "vs")
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(set_attr "length" "8")])
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[(set_attr "length" "8")
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(set_attr "type" "vs")])
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(define_expand "strlensi"
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[(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
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@ -1840,9 +1836,8 @@
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(clobber (reg:CC 33))]
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"!TARGET_64BIT"
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"srst\t%0,%1\;jo\t.-4"
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[(set_attr "op_type" "NN")
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(set_attr "type" "vs")
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(set_attr "length" "8")])
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[(set_attr "length" "8")
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(set_attr "type" "vs")])
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;
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; movmemM instruction pattern(s).
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@ -1886,8 +1881,7 @@
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"(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
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&& GET_MODE (operands[4]) == Pmode"
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"#"
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[(set_attr "op_type" "SS,RX,RX")
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(set_attr "type" "cs")])
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[(set_attr "type" "cs")])
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(define_split
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[(set (match_operand:BLK 0 "memory_operand" "")
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@ -1975,9 +1969,8 @@
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(clobber (reg:CC 33))]
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"TARGET_64BIT"
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"mvcle\t%0,%1,0\;jo\t.-4"
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[(set_attr "op_type" "NN")
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(set_attr "type" "vs")
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(set_attr "length" "8")])
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[(set_attr "length" "8")
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(set_attr "type" "vs")])
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(define_insn "*movmem_long_31"
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[(clobber (match_operand:DI 0 "register_operand" "=d"))
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@ -1989,9 +1982,8 @@
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(clobber (reg:CC 33))]
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"!TARGET_64BIT"
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"mvcle\t%0,%1,0\;jo\t.-4"
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[(set_attr "op_type" "NN")
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(set_attr "type" "vs")
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(set_attr "length" "8")])
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[(set_attr "length" "8")
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(set_attr "type" "vs")])
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;
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; clrmemM instruction pattern(s).
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@ -2037,8 +2029,7 @@
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"(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
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&& GET_MODE (operands[3]) == Pmode"
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"#"
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[(set_attr "op_type" "SS,RX,RX")
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(set_attr "type" "cs")])
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[(set_attr "type" "cs")])
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(define_split
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[(set (match_operand:BLK 0 "memory_operand" "")
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@ -2125,9 +2116,8 @@
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(clobber (reg:CC 33))]
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"TARGET_64BIT"
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"mvcle\t%0,%1,0\;jo\t.-4"
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[(set_attr "op_type" "NN")
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(set_attr "type" "vs")
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(set_attr "length" "8")])
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[(set_attr "length" "8")
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(set_attr "type" "vs")])
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(define_insn "*clrmem_long_31"
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[(clobber (match_operand:DI 0 "register_operand" "=d"))
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@ -2138,9 +2128,8 @@
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(clobber (reg:CC 33))]
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"!TARGET_64BIT"
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"mvcle\t%0,%1,0\;jo\t.-4"
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[(set_attr "op_type" "NN")
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(set_attr "type" "vs")
|
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(set_attr "length" "8")])
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[(set_attr "length" "8")
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(set_attr "type" "vs")])
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;
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; cmpmemM instruction pattern(s).
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@ -2180,8 +2169,7 @@
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"(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
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&& GET_MODE (operands[4]) == Pmode"
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"#"
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[(set_attr "op_type" "SS,RX,RX")
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(set_attr "type" "cs")])
|
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[(set_attr "type" "cs")])
|
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|
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(define_split
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[(set (reg:CCU 33)
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@ -2272,9 +2260,8 @@
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(use (match_dup 3))]
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"TARGET_64BIT"
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"clcle\t%0,%1,0\;jo\t.-4"
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[(set_attr "op_type" "NN")
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(set_attr "type" "vs")
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(set_attr "length" "8")])
|
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[(set_attr "length" "8")
|
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(set_attr "type" "vs")])
|
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|
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(define_insn "*cmpmem_long_31"
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[(clobber (match_operand:DI 0 "register_operand" "=d"))
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@ -2286,9 +2273,8 @@
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(use (match_dup 3))]
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"!TARGET_64BIT"
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"clcle\t%0,%1,0\;jo\t.-4"
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[(set_attr "op_type" "NN")
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(set_attr "type" "vs")
|
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(set_attr "length" "8")])
|
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[(set_attr "length" "8")
|
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(set_attr "type" "vs")])
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|
||||
; Convert condition code to integer in range (-1, 0, 1)
|
||||
|
||||
@ -2303,9 +2289,7 @@
|
||||
output_asm_insn ("sr\t%0,%0", operands);
|
||||
return "lcr\t%0,%0";
|
||||
}
|
||||
[(set_attr "op_type" "NN")
|
||||
(set_attr "length" "16")
|
||||
(set_attr "type" "other")])
|
||||
[(set_attr "length" "16")])
|
||||
|
||||
(define_insn "*cmpint_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
@ -2318,9 +2302,7 @@
|
||||
output_asm_insn ("sgr\t%0,%0", operands);
|
||||
return "lcgr\t%0,%0";
|
||||
}
|
||||
[(set_attr "op_type" "NN")
|
||||
(set_attr "length" "20")
|
||||
(set_attr "type" "other")])
|
||||
[(set_attr "length" "20")])
|
||||
|
||||
|
||||
;;
|
||||
@ -2382,8 +2364,7 @@
|
||||
{
|
||||
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
|
||||
operands[1] = change_address (operands[1], QImode, 0);
|
||||
}
|
||||
[(set_attr "atype" "agen")])
|
||||
})
|
||||
|
||||
(define_insn_and_split "*extracthi"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
@ -2402,8 +2383,7 @@
|
||||
{
|
||||
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
|
||||
operands[1] = change_address (operands[1], HImode, 0);
|
||||
}
|
||||
[(set_attr "atype" "agen")])
|
||||
})
|
||||
|
||||
;
|
||||
; extendsidi2 instruction pattern(s).
|
||||
@ -2786,8 +2766,7 @@
|
||||
(parallel
|
||||
[(set (strict_low_part (match_dup 2)) (match_dup 1))
|
||||
(clobber (reg:CC 33))])]
|
||||
"operands[2] = gen_lowpart (HImode, operands[0]);"
|
||||
[(set_attr "atype" "agen")])
|
||||
"operands[2] = gen_lowpart (HImode, operands[0]);")
|
||||
|
||||
;
|
||||
; zero_extendqisi2 instruction pattern(s).
|
||||
@ -2820,8 +2799,7 @@
|
||||
"&& reload_completed"
|
||||
[(set (match_dup 0) (const_int 0))
|
||||
(set (strict_low_part (match_dup 2)) (match_dup 1))]
|
||||
"operands[2] = gen_lowpart (QImode, operands[0]);"
|
||||
[(set_attr "atype" "agen")])
|
||||
"operands[2] = gen_lowpart (QImode, operands[0]);")
|
||||
|
||||
;
|
||||
; zero_extendqihi2 instruction pattern(s).
|
||||
@ -2854,8 +2832,7 @@
|
||||
"&& reload_completed"
|
||||
[(set (match_dup 0) (const_int 0))
|
||||
(set (strict_low_part (match_dup 2)) (match_dup 1))]
|
||||
"operands[2] = gen_lowpart (QImode, operands[0]);"
|
||||
[(set_attr "atype" "agen")])
|
||||
"operands[2] = gen_lowpart (QImode, operands[0]);")
|
||||
|
||||
|
||||
;
|
||||
@ -2989,10 +2966,7 @@
|
||||
output_asm_insn ("xi\t%N4,128", operands);
|
||||
return "l\t%0,%N4";
|
||||
}
|
||||
[(set_attr "op_type" "NN")
|
||||
(set_attr "type" "other")
|
||||
(set_attr "atype" "agen")
|
||||
(set_attr "length" "20")])
|
||||
[(set_attr "length" "20")])
|
||||
|
||||
;
|
||||
; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
|
||||
@ -3173,10 +3147,7 @@
|
||||
output_asm_insn ("ld\t%0,%3", operands);
|
||||
return "sd\t%0,%2";
|
||||
}
|
||||
[(set_attr "op_type" "NN")
|
||||
(set_attr "type" "other" )
|
||||
(set_attr "atype" "agen")
|
||||
(set_attr "length" "20")])
|
||||
[(set_attr "length" "20")])
|
||||
|
||||
;
|
||||
; floatsisf2 instruction pattern(s).
|
||||
@ -3266,8 +3237,7 @@
|
||||
"@
|
||||
sdr\t%0,%0\;ler\t%0,%1
|
||||
sdr\t%0,%0\;le\t%0,%1"
|
||||
[(set_attr "op_type" "NN,NN")
|
||||
(set_attr "length" "4,6")
|
||||
[(set_attr "length" "4,6")
|
||||
(set_attr "type" "floads,floads")])
|
||||
|
||||
|
||||
@ -3308,8 +3278,7 @@
|
||||
operands[5] = operand_subword (operands[2], 0, 0, TImode);
|
||||
operands[6] = operand_subword (operands[0], 1, 0, TImode);
|
||||
operands[7] = operand_subword (operands[1], 1, 0, TImode);
|
||||
operands[8] = operand_subword (operands[2], 1, 0, TImode);"
|
||||
[(set_attr "op_type" "NN")])
|
||||
operands[8] = operand_subword (operands[2], 1, 0, TImode);")
|
||||
|
||||
;
|
||||
; adddi3 instruction pattern(s).
|
||||
@ -3495,8 +3464,7 @@
|
||||
operands[5] = operand_subword (operands[2], 0, 0, DImode);
|
||||
operands[6] = operand_subword (operands[0], 1, 0, DImode);
|
||||
operands[7] = operand_subword (operands[1], 1, 0, DImode);
|
||||
operands[8] = operand_subword (operands[2], 1, 0, DImode);"
|
||||
[(set_attr "op_type" "NN")])
|
||||
operands[8] = operand_subword (operands[2], 1, 0, DImode);")
|
||||
|
||||
(define_insn_and_split "*adddi3_31"
|
||||
[(set (match_operand:DI 0 "register_operand" "=&d")
|
||||
@ -3528,8 +3496,7 @@
|
||||
operands[6] = operand_subword (operands[0], 1, 0, DImode);
|
||||
operands[7] = operand_subword (operands[1], 1, 0, DImode);
|
||||
operands[8] = operand_subword (operands[2], 1, 0, DImode);
|
||||
operands[9] = gen_label_rtx ();"
|
||||
[(set_attr "op_type" "NN")])
|
||||
operands[9] = gen_label_rtx ();")
|
||||
|
||||
(define_expand "adddi3"
|
||||
[(parallel
|
||||
@ -3832,8 +3799,7 @@
|
||||
operands[5] = operand_subword (operands[2], 0, 0, TImode);
|
||||
operands[6] = operand_subword (operands[0], 1, 0, TImode);
|
||||
operands[7] = operand_subword (operands[1], 1, 0, TImode);
|
||||
operands[8] = operand_subword (operands[2], 1, 0, TImode);"
|
||||
[(set_attr "op_type" "NN")])
|
||||
operands[8] = operand_subword (operands[2], 1, 0, TImode);")
|
||||
|
||||
;
|
||||
; subdi3 instruction pattern(s).
|
||||
@ -3992,8 +3958,7 @@
|
||||
operands[5] = operand_subword (operands[2], 0, 0, DImode);
|
||||
operands[6] = operand_subword (operands[0], 1, 0, DImode);
|
||||
operands[7] = operand_subword (operands[1], 1, 0, DImode);
|
||||
operands[8] = operand_subword (operands[2], 1, 0, DImode);"
|
||||
[(set_attr "op_type" "NN")])
|
||||
operands[8] = operand_subword (operands[2], 1, 0, DImode);")
|
||||
|
||||
(define_insn_and_split "*subdi3_31"
|
||||
[(set (match_operand:DI 0 "register_operand" "=&d")
|
||||
@ -4025,8 +3990,7 @@
|
||||
operands[6] = operand_subword (operands[0], 1, 0, DImode);
|
||||
operands[7] = operand_subword (operands[1], 1, 0, DImode);
|
||||
operands[8] = operand_subword (operands[2], 1, 0, DImode);
|
||||
operands[9] = gen_label_rtx ();"
|
||||
[(set_attr "op_type" "NN")])
|
||||
operands[9] = gen_label_rtx ();")
|
||||
|
||||
(define_expand "subdi3"
|
||||
[(parallel
|
||||
@ -4431,8 +4395,7 @@
|
||||
[(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
|
||||
(match_dup 1)))
|
||||
(clobber (reg:CC 33))])]
|
||||
""
|
||||
[(set_attr "op_type" "NN")])
|
||||
"")
|
||||
|
||||
(define_insn_and_split "*scondsi"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d")
|
||||
@ -4446,8 +4409,7 @@
|
||||
[(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
|
||||
(match_dup 1)))
|
||||
(clobber (reg:CC 33))])]
|
||||
""
|
||||
[(set_attr "op_type" "NN")])
|
||||
"")
|
||||
|
||||
(define_insn_and_split "*sconddi_neg"
|
||||
[(set (match_operand:DI 0 "register_operand" "=&d")
|
||||
@ -4464,8 +4426,7 @@
|
||||
(parallel
|
||||
[(set (match_dup 0) (neg:DI (match_dup 0)))
|
||||
(clobber (reg:CC 33))])]
|
||||
""
|
||||
[(set_attr "op_type" "NN")])
|
||||
"")
|
||||
|
||||
(define_insn_and_split "*scondsi_neg"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&d")
|
||||
@ -4482,8 +4443,7 @@
|
||||
(parallel
|
||||
[(set (match_dup 0) (neg:SI (match_dup 0)))
|
||||
(clobber (reg:CC 33))])]
|
||||
""
|
||||
[(set_attr "op_type" "NN")])
|
||||
"")
|
||||
|
||||
(define_expand "sltu"
|
||||
[(match_operand:SI 0 "register_operand" "")]
|
||||
@ -5473,8 +5433,7 @@
|
||||
(clobber (reg:CC 33))]
|
||||
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
|
||||
"nc\t%O0(%2,%R0),%S1"
|
||||
[(set_attr "op_type" "SS")
|
||||
(set_attr "type" "cs")])
|
||||
[(set_attr "op_type" "SS")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand 0 "memory_operand" "")
|
||||
@ -5763,8 +5722,7 @@
|
||||
(clobber (reg:CC 33))]
|
||||
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
|
||||
"oc\t%O0(%2,%R0),%S1"
|
||||
[(set_attr "op_type" "SS")
|
||||
(set_attr "type" "cs")])
|
||||
[(set_attr "op_type" "SS")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand 0 "memory_operand" "")
|
||||
@ -6007,8 +5965,7 @@
|
||||
(clobber (reg:CC 33))]
|
||||
"INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
|
||||
"xc\t%O0(%2,%R0),%S1"
|
||||
[(set_attr "op_type" "SS")
|
||||
(set_attr "type" "cs")])
|
||||
[(set_attr "op_type" "SS")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand 0 "memory_operand" "")
|
||||
@ -6063,8 +6020,7 @@
|
||||
(clobber (reg:CC 33))]
|
||||
"INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
|
||||
"xc\t%O0(%1,%R0),%S0"
|
||||
[(set_attr "op_type" "SS")
|
||||
(set_attr "type" "cs")])
|
||||
[(set_attr "op_type" "SS")])
|
||||
|
||||
(define_peephole2
|
||||
[(parallel
|
||||
@ -6127,9 +6083,7 @@
|
||||
CODE_LABEL_NUMBER (xop[0]));
|
||||
return "";
|
||||
}
|
||||
[(set_attr "op_type" "NN")
|
||||
(set_attr "type" "other")
|
||||
(set_attr "length" "10")])
|
||||
[(set_attr "length" "10")])
|
||||
|
||||
;
|
||||
; negsi2 instruction pattern(s).
|
||||
@ -7721,8 +7675,7 @@
|
||||
s390_output_pool_entry (operands[0], mode, align);
|
||||
return "";
|
||||
}
|
||||
[(set_attr "op_type" "NN")
|
||||
(set (attr "length")
|
||||
[(set (attr "length")
|
||||
(symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
|
||||
|
||||
(define_insn "pool_align"
|
||||
@ -7730,22 +7683,19 @@
|
||||
UNSPECV_POOL_ALIGN)]
|
||||
""
|
||||
".align\t%0"
|
||||
[(set_attr "op_type" "NN")
|
||||
(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
|
||||
[(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
|
||||
|
||||
(define_insn "pool_section_start"
|
||||
[(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
|
||||
""
|
||||
".section\t.rodata"
|
||||
[(set_attr "op_type" "NN")
|
||||
(set_attr "length" "0")])
|
||||
[(set_attr "length" "0")])
|
||||
|
||||
(define_insn "pool_section_end"
|
||||
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
|
||||
""
|
||||
".previous"
|
||||
[(set_attr "op_type" "NN")
|
||||
(set_attr "length" "0")])
|
||||
[(set_attr "length" "0")])
|
||||
|
||||
(define_insn "main_base_31_small"
|
||||
[(set (match_operand 0 "register_operand" "=a")
|
||||
@ -7776,8 +7726,7 @@
|
||||
(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
|
||||
"GET_MODE (operands[0]) == Pmode"
|
||||
"* abort ();"
|
||||
[(set_attr "op_type" "NN")
|
||||
(set (attr "type")
|
||||
[(set (attr "type")
|
||||
(if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
|
||||
(const_string "larl") (const_string "la")))])
|
||||
|
||||
@ -7786,9 +7735,8 @@
|
||||
(unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
|
||||
"!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
|
||||
"basr\t%0,0\;la\t%0,%1-.(%0)"
|
||||
[(set_attr "op_type" "NN")
|
||||
(set_attr "type" "la")
|
||||
(set_attr "length" "6")])
|
||||
[(set_attr "length" "6")
|
||||
(set_attr "type" "la")])
|
||||
|
||||
(define_insn "reload_base_64"
|
||||
[(set (match_operand 0 "register_operand" "=a")
|
||||
@ -7802,8 +7750,7 @@
|
||||
[(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
|
||||
""
|
||||
"* abort ();"
|
||||
[(set_attr "op_type" "NN")
|
||||
(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
|
||||
[(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
|
||||
|
||||
;;
|
||||
;; Insns related to generating the function prologue and epilogue.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user