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* config/i386/i386.md: Rearrange divmod patterns a bit.
From-SVN: r164347
This commit is contained in:
Uros Bizjak
parent
26ec93086a
commit
b3df2256e7
@ -7154,125 +7154,6 @@
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;; Divmod instructions.
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(define_expand "divmodqi4"
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[(parallel [(set (match_operand:QI 0 "register_operand" "")
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(div:QI
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(match_operand:QI 1 "register_operand" "")
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(match_operand:QI 2 "nonimmediate_operand" "")))
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(set (match_operand:QI 3 "register_operand" "")
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(mod:QI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_QIMODE_MATH"
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{
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rtx div, mod, insn;
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rtx tmp0, tmp1;
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tmp0 = gen_reg_rtx (HImode);
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tmp1 = gen_reg_rtx (HImode);
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/* Extend operands[1] to HImode. Generate 8bit divide. Result is
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in AX. */
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emit_insn (gen_extendqihi2 (tmp1, operands[1]));
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emit_insn (gen_divmodhiqi3 (tmp0, tmp1, operands[2]));
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/* Extract remainder from AH. */
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tmp1 = gen_rtx_SIGN_EXTRACT (QImode, tmp0, GEN_INT (8), GEN_INT (8));
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insn = emit_move_insn (operands[3], tmp1);
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mod = gen_rtx_MOD (QImode, operands[1], operands[2]);
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set_unique_reg_note (insn, REG_EQUAL, mod);
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/* Extract quotient from AL. */
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insn = emit_move_insn (operands[0], gen_lowpart (QImode, tmp0));
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div = gen_rtx_DIV (QImode, operands[1], operands[2]);
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set_unique_reg_note (insn, REG_EQUAL, div);
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DONE;
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})
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(define_expand "udivmodqi4"
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[(parallel [(set (match_operand:QI 0 "register_operand" "")
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(udiv:QI
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(match_operand:QI 1 "register_operand" "")
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(match_operand:QI 2 "nonimmediate_operand" "")))
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(set (match_operand:QI 3 "register_operand" "")
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(umod:QI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_QIMODE_MATH"
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{
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rtx div, mod, insn;
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rtx tmp0, tmp1;
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tmp0 = gen_reg_rtx (HImode);
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tmp1 = gen_reg_rtx (HImode);
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/* Extend operands[1] to HImode. Generate 8bit divide. Result is
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in AX. */
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emit_insn (gen_zero_extendqihi2 (tmp1, operands[1]));
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emit_insn (gen_udivmodhiqi3 (tmp0, tmp1, operands[2]));
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/* Extract remainder from AH. */
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tmp1 = gen_rtx_ZERO_EXTRACT (SImode, tmp0, GEN_INT (8), GEN_INT (8));
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tmp1 = simplify_gen_subreg (QImode, tmp1, SImode, 0);
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insn = emit_move_insn (operands[3], tmp1);
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mod = gen_rtx_UMOD (QImode, operands[1], operands[2]);
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set_unique_reg_note (insn, REG_EQUAL, mod);
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/* Extract quotient from AL. */
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insn = emit_move_insn (operands[0], gen_lowpart (QImode, tmp0));
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div = gen_rtx_UDIV (QImode, operands[1], operands[2]);
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set_unique_reg_note (insn, REG_EQUAL, div);
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DONE;
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})
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;; Divide AX by r/m8, with result stored in
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;; AL <- Quotient
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;; AH <- Remainder
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;; Change div/mod to HImode and extend the second argument to HImode
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;; so that mode of div/mod matches with mode of arguments. Otherwise
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;; combine may fail.
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(define_insn "divmodhiqi3"
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[(set (match_operand:HI 0 "register_operand" "=a")
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(ior:HI
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(ashift:HI
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(zero_extend:HI
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(truncate:QI
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(mod:HI (match_operand:HI 1 "register_operand" "0")
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(sign_extend:HI
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(match_operand:QI 2 "nonimmediate_operand" "qm")))))
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(const_int 8))
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(zero_extend:HI
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(truncate:QI
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(div:HI (match_dup 1) (sign_extend:HI (match_dup 2)))))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_QIMODE_MATH"
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"idiv{b}\t%2"
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[(set_attr "type" "idiv")
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(set_attr "mode" "QI")])
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(define_insn "udivmodhiqi3"
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[(set (match_operand:HI 0 "register_operand" "=a")
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(ior:HI
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(ashift:HI
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(zero_extend:HI
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(truncate:QI
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(mod:HI (match_operand:HI 1 "register_operand" "0")
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(zero_extend:HI
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(match_operand:QI 2 "nonimmediate_operand" "qm")))))
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(const_int 8))
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(zero_extend:HI
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(truncate:QI
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(div:HI (match_dup 1) (zero_extend:HI (match_dup 2)))))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_QIMODE_MATH"
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"div{b}\t%2"
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[(set_attr "type" "idiv")
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(set_attr "mode" "QI")])
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(define_expand "divmod<mode>4"
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[(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
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(div:SWIM248
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@ -7282,41 +7163,6 @@
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(mod:SWIM248 (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])])
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(define_insn_and_split "*divmod<mode>4"
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[(set (match_operand:SWIM248 0 "register_operand" "=a")
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(div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
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(match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
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(set (match_operand:SWIM248 1 "register_operand" "=&d")
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(mod:SWIM248 (match_dup 2) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))]
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""
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"#"
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"reload_completed"
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[(parallel [(set (match_dup 1)
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(ashiftrt:SWIM248 (match_dup 4) (match_dup 5)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel [(set (match_dup 0)
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(div:SWIM248 (match_dup 2) (match_dup 3)))
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(set (match_dup 1)
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(mod:SWIM248 (match_dup 2) (match_dup 3)))
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(use (match_dup 1))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
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if (<MODE>mode != HImode
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&& (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD))
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operands[4] = operands[2];
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else
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{
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/* Avoid use of cltd in favor of a mov+shift. */
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emit_move_insn (operands[1], operands[2]);
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operands[4] = operands[1];
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}
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}
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[(set_attr "type" "multi")
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(set_attr "mode" "<MODE>")])
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;; Split with 8bit unsigned divide:
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;; if (dividend an divisor are in [0-255])
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;; use 8bit unsigned integer divide
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@ -7371,6 +7217,41 @@
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[(set_attr "type" "multi")
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(set_attr "mode" "<MODE>")])
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(define_insn_and_split "*divmod<mode>4"
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[(set (match_operand:SWIM248 0 "register_operand" "=a")
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(div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
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(match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
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(set (match_operand:SWIM248 1 "register_operand" "=&d")
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(mod:SWIM248 (match_dup 2) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))]
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""
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"#"
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"reload_completed"
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[(parallel [(set (match_dup 1)
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(ashiftrt:SWIM248 (match_dup 4) (match_dup 5)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel [(set (match_dup 0)
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(div:SWIM248 (match_dup 2) (match_dup 3)))
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(set (match_dup 1)
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(mod:SWIM248 (match_dup 2) (match_dup 3)))
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(use (match_dup 1))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
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if (<MODE>mode != HImode
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&& (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD))
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operands[4] = operands[2];
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else
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{
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/* Avoid use of cltd in favor of a mov+shift. */
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emit_move_insn (operands[1], operands[2]);
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operands[4] = operands[1];
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}
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}
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[(set_attr "type" "multi")
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(set_attr "mode" "<MODE>")])
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(define_insn "*divmod<mode>4_noext"
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[(set (match_operand:SWIM248 0 "register_operand" "=a")
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(div:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
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@ -7384,6 +7265,68 @@
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[(set_attr "type" "idiv")
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(set_attr "mode" "<MODE>")])
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(define_expand "divmodqi4"
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[(parallel [(set (match_operand:QI 0 "register_operand" "")
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(div:QI
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(match_operand:QI 1 "register_operand" "")
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(match_operand:QI 2 "nonimmediate_operand" "")))
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(set (match_operand:QI 3 "register_operand" "")
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(mod:QI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_QIMODE_MATH"
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{
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rtx div, mod, insn;
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rtx tmp0, tmp1;
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tmp0 = gen_reg_rtx (HImode);
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tmp1 = gen_reg_rtx (HImode);
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/* Extend operands[1] to HImode. Generate 8bit divide. Result is
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in AX. */
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emit_insn (gen_extendqihi2 (tmp1, operands[1]));
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emit_insn (gen_divmodhiqi3 (tmp0, tmp1, operands[2]));
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/* Extract remainder from AH. */
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tmp1 = gen_rtx_SIGN_EXTRACT (QImode, tmp0, GEN_INT (8), GEN_INT (8));
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insn = emit_move_insn (operands[3], tmp1);
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mod = gen_rtx_MOD (QImode, operands[1], operands[2]);
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set_unique_reg_note (insn, REG_EQUAL, mod);
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/* Extract quotient from AL. */
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insn = emit_move_insn (operands[0], gen_lowpart (QImode, tmp0));
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div = gen_rtx_DIV (QImode, operands[1], operands[2]);
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set_unique_reg_note (insn, REG_EQUAL, div);
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DONE;
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})
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;; Divide AX by r/m8, with result stored in
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;; AL <- Quotient
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;; AH <- Remainder
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;; Change div/mod to HImode and extend the second argument to HImode
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;; so that mode of div/mod matches with mode of arguments. Otherwise
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;; combine may fail.
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(define_insn "divmodhiqi3"
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[(set (match_operand:HI 0 "register_operand" "=a")
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(ior:HI
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(ashift:HI
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(zero_extend:HI
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(truncate:QI
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(mod:HI (match_operand:HI 1 "register_operand" "0")
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(sign_extend:HI
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(match_operand:QI 2 "nonimmediate_operand" "qm")))))
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(const_int 8))
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(zero_extend:HI
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(truncate:QI
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(div:HI (match_dup 1) (sign_extend:HI (match_dup 2)))))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_QIMODE_MATH"
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"idiv{b}\t%2"
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[(set_attr "type" "idiv")
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(set_attr "mode" "QI")])
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(define_expand "udivmod<mode>4"
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[(parallel [(set (match_operand:SWIM248 0 "register_operand" "")
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(udiv:SWIM248
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@ -7393,27 +7336,6 @@
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(umod:SWIM248 (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])])
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(define_insn_and_split "*udivmod<mode>4"
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[(set (match_operand:SWIM248 0 "register_operand" "=a")
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(udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
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(match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
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(set (match_operand:SWIM248 1 "register_operand" "=&d")
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(umod:SWIM248 (match_dup 2) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))]
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""
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"#"
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"reload_completed"
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[(set (match_dup 1) (const_int 0))
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(parallel [(set (match_dup 0)
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(udiv:SWIM248 (match_dup 2) (match_dup 3)))
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(set (match_dup 1)
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(umod:SWIM248 (match_dup 2) (match_dup 3)))
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(use (match_dup 1))
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(clobber (reg:CC FLAGS_REG))])]
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""
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[(set_attr "type" "multi")
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(set_attr "mode" "<MODE>")])
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;; Split with 8bit unsigned divide:
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;; if (dividend an divisor are in [0-255])
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;; use 8bit unsigned integer divide
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@ -7455,6 +7377,27 @@
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[(set_attr "type" "multi")
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(set_attr "mode" "<MODE>")])
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(define_insn_and_split "*udivmod<mode>4"
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[(set (match_operand:SWIM248 0 "register_operand" "=a")
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(udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
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(match_operand:SWIM248 3 "nonimmediate_operand" "rm")))
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(set (match_operand:SWIM248 1 "register_operand" "=&d")
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(umod:SWIM248 (match_dup 2) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))]
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""
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"#"
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"reload_completed"
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[(set (match_dup 1) (const_int 0))
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(parallel [(set (match_dup 0)
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(udiv:SWIM248 (match_dup 2) (match_dup 3)))
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(set (match_dup 1)
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(umod:SWIM248 (match_dup 2) (match_dup 3)))
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(use (match_dup 1))
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(clobber (reg:CC FLAGS_REG))])]
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""
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[(set_attr "type" "multi")
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(set_attr "mode" "<MODE>")])
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(define_insn "*udivmod<mode>4_noext"
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[(set (match_operand:SWIM248 0 "register_operand" "=a")
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(udiv:SWIM248 (match_operand:SWIM248 2 "register_operand" "0")
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@ -7468,6 +7411,63 @@
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[(set_attr "type" "idiv")
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(set_attr "mode" "<MODE>")])
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(define_expand "udivmodqi4"
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[(parallel [(set (match_operand:QI 0 "register_operand" "")
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(udiv:QI
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(match_operand:QI 1 "register_operand" "")
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(match_operand:QI 2 "nonimmediate_operand" "")))
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(set (match_operand:QI 3 "register_operand" "")
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(umod:QI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_QIMODE_MATH"
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{
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rtx div, mod, insn;
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rtx tmp0, tmp1;
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tmp0 = gen_reg_rtx (HImode);
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tmp1 = gen_reg_rtx (HImode);
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/* Extend operands[1] to HImode. Generate 8bit divide. Result is
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in AX. */
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emit_insn (gen_zero_extendqihi2 (tmp1, operands[1]));
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emit_insn (gen_udivmodhiqi3 (tmp0, tmp1, operands[2]));
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/* Extract remainder from AH. */
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tmp1 = gen_rtx_ZERO_EXTRACT (SImode, tmp0, GEN_INT (8), GEN_INT (8));
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tmp1 = simplify_gen_subreg (QImode, tmp1, SImode, 0);
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insn = emit_move_insn (operands[3], tmp1);
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mod = gen_rtx_UMOD (QImode, operands[1], operands[2]);
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set_unique_reg_note (insn, REG_EQUAL, mod);
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/* Extract quotient from AL. */
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insn = emit_move_insn (operands[0], gen_lowpart (QImode, tmp0));
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div = gen_rtx_UDIV (QImode, operands[1], operands[2]);
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set_unique_reg_note (insn, REG_EQUAL, div);
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DONE;
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})
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(define_insn "udivmodhiqi3"
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[(set (match_operand:HI 0 "register_operand" "=a")
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(ior:HI
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(ashift:HI
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(zero_extend:HI
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(truncate:QI
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(mod:HI (match_operand:HI 1 "register_operand" "0")
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(zero_extend:HI
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(match_operand:QI 2 "nonimmediate_operand" "qm")))))
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(const_int 8))
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(zero_extend:HI
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(truncate:QI
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(div:HI (match_dup 1) (zero_extend:HI (match_dup 2)))))))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_QIMODE_MATH"
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"div{b}\t%2"
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[(set_attr "type" "idiv")
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(set_attr "mode" "QI")])
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;; We cannot use div/idiv for double division, because it causes
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;; "division by zero" on the overflow and that's not what we expect
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;; from truncate. Because true (non truncating) double division is
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