mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-03-26 21:51:12 +08:00
Code Issues Packages Projects Releases Wiki Activity

rx.md: Add peepholes to match a register move followed by a comparison of the moved...

Browse Source 
* config/rx/rx.md: Add peepholes to match a register move followed
	by a comparison of the moved register.  Replace these with an
	addition of zero that does both actions in one instruction.

Co-Authored-By: Nick Clifton <nickc@redhat.com>

From-SVN: r173819
This commit is contained in:
Kazuhio Inaoka 2011-05-17 08:27:40 +00:00 committed by Nick Clifton
parent f3450bc8d8
commit b3db92ac19
2 changed files with 40 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2011-05-17 Kazuhio Inaoka <kazuhiro.inaoka.ud@renesas.com>
Nick Clifton <nickc@redhat.com>
* config/rx/rx.md: Add peepholes to match a register move followed
by a comparison of the moved register. Replace these with an
addition of zero that does both actions in one instruction.
2011-05-17 Jakub Jelinek <jakub@redhat.com>
PR target/48986

33
gcc/config/rx/rx.md
View File

@ -904,6 +904,39 @@
(set_attr "length" "3,4,5,6,7,6")]
)
;; Peepholes to match:
;; (set (reg A) (reg B))
;; (set (CC) (compare:CC (reg A/reg B) (const_int 0)))
;; and replace them with the addsi3_flags pattern, using an add
;; of zero to copy the register and set the condition code bits.
(define_peephole2
[(set (match_operand:SI 0 "register_operand")
(match_operand:SI 1 "register_operand"))
(set (reg:CC CC_REG)
(compare:CC (match_dup 0)
(const_int 0)))]
""
[(parallel [(set (match_dup 0)
(plus:SI (match_dup 1) (const_int 0)))
(set (reg:CC_ZSC CC_REG)
(compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
(const_int 0)))])]
)
(define_peephole2
[(set (match_operand:SI 0 "register_operand")
(match_operand:SI 1 "register_operand"))
(set (reg:CC CC_REG)
(compare:CC (match_dup 1)
(const_int 0)))]
""
[(parallel [(set (match_dup 0)
(plus:SI (match_dup 1) (const_int 0)))
(set (reg:CC_ZSC CC_REG)
(compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
(const_int 0)))])]
)
(define_expand "adddi3"
[(set (match_operand:DI 0 "register_operand")
(plus:DI (match_operand:DI 1 "register_operand")