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recog.c (recog_memoized): Rename to recog_memoized_1.
* recog.c (recog_memoized): Rename to recog_memoized_1. * recog.h (recog_memoized): Rename to recog_memoized_1. (recog_memoized): New macro. * rtl.h (single_set): Rename to single_set_1 (single_set): New macro. * rtlanal.c (single_set): Rename to single_set_1; expect clobbers to be last. * i386.md (strmovsi_1, strmovhi_1 strmovqi_1): Do not use match_dup of input operands at outputs. Use register_operand for memory expression. (rep_movsi): Put use last, canonicalize. Use register_operand for memory expression. (rep_movqi): Put use last. Use register_operand for memory expression. (strsetsi_1, strset_hi_1, strsetqi_1): Do not use match_dup of input operands at outputs. Use register_operand for memory expression. (rep_stossi): Put use last; canonicalize; fix match_dup in the address expression (rep_stosqi): Likewise. (memcmp expander): Update calls. (cmpstrsi_nz_1, cmpstrsi_1, strlensi_1): Avoid match_dups in the clobbers. * i386.md (fp_jcc_3, fp_jcc_4, jp_fcc_5): if_then_else operand is VOIDmode. (fp_jcc_4, fp_jcc_3): Refuse unordered comparisons. From-SVN: r36664
This commit is contained in:
Jan Hubicka
parent
073427934a
commit
b1cdafbb6c
@ -125,6 +125,7 @@ extern int ix86_adjust_cost PARAMS ((rtx, rtx, rtx, int));
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extern void ix86_sched_init PARAMS ((FILE *, int));
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extern int ix86_sched_reorder PARAMS ((FILE *, int, rtx *, int, int));
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extern int ix86_variable_issue PARAMS ((FILE *, int, rtx, int));
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extern enum machine_mode ix86_fp_compare_mode PARAMS ((enum rtx_code));
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#ifdef TREE_CODE
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extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *, tree, rtx));
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@ -388,7 +388,6 @@ static void put_condition_code PARAMS ((enum rtx_code, enum machine_mode,
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int, int, FILE *));
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static enum rtx_code unsigned_comparison PARAMS ((enum rtx_code code));
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static rtx ix86_expand_int_compare PARAMS ((enum rtx_code, rtx, rtx));
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static enum machine_mode ix86_fp_compare_mode PARAMS ((enum rtx_code));
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static enum rtx_code ix86_prepare_fp_compare_args PARAMS ((enum rtx_code,
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rtx *, rtx *));
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static rtx gen_push PARAMS ((rtx));
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@ -4635,7 +4634,7 @@ ix86_expand_int_compare (code, op0, op1)
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/* Figure out whether to use ordered or unordered fp comparisons.
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Return the appropriate mode to use. */
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static enum machine_mode
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enum machine_mode
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ix86_fp_compare_mode (code)
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enum rtx_code code;
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{
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@ -8539,7 +8539,7 @@
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(define_insn "*fp_jcc_3"
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[(set (pc)
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(if_then_else (match_operator:CCFP 0 "comparison_operator"
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(if_then_else (match_operator 0 "comparison_operator"
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[(match_operand 1 "register_operand" "f")
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(match_operand 2 "nonimmediate_operand" "fm")])
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(label_ref (match_operand 3 "" ""))
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@ -8550,12 +8550,14 @@
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"TARGET_80387
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&& (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
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&& GET_MODE (operands[1]) == GET_MODE (operands[2])
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&& !ix86_use_fcomi_compare (GET_CODE (operands[0]))"
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&& !ix86_use_fcomi_compare (GET_CODE (operands[0]))
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&& SELECT_CC_MODE (GET_CODE (operands[0]),
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operands[1], operands[2]) == CCFPmode"
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"#")
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(define_insn "*fp_jcc_4"
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[(set (pc)
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(if_then_else (match_operator:CCFP 0 "comparison_operator"
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(if_then_else (match_operator 0 "comparison_operator"
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[(match_operand 1 "register_operand" "f")
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(match_operand 2 "nonimmediate_operand" "fm")])
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(pc)
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@ -8566,7 +8568,9 @@
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"TARGET_80387
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&& (GET_MODE (operands[1]) == SFmode || GET_MODE (operands[1]) == DFmode)
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&& GET_MODE (operands[1]) == GET_MODE (operands[2])
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&& !ix86_use_fcomi_compare (GET_CODE (operands[0]))"
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&& !ix86_use_fcomi_compare (GET_CODE (operands[0]))
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&& SELECT_CC_MODE (GET_CODE (operands[0]),
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operands[1], operands[2]) == CCFPmode"
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"#")
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(define_insn "*fp_jcc_5"
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@ -10003,10 +10007,10 @@
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[(set (mem:SI (match_operand:SI 2 "register_operand" "0"))
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(mem:SI (match_operand:SI 3 "register_operand" "1")))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_dup 0)
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(plus:SI (match_dup 2)
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(const_int 4)))
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(set (match_operand:SI 1 "register_operand" "=S")
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(plus:SI (match_dup 1)
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(plus:SI (match_dup 3)
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(const_int 4)))
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(use (reg:SI 19))]
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"TARGET_SINGLE_STRINGOP || optimize_size"
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@ -10019,10 +10023,10 @@
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[(set (mem:HI (match_operand:SI 2 "register_operand" "0"))
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(mem:HI (match_operand:SI 3 "register_operand" "1")))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_dup 0)
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(plus:SI (match_dup 2)
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(const_int 2)))
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(set (match_operand:SI 1 "register_operand" "=S")
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(plus:SI (match_dup 1)
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(plus:SI (match_dup 3)
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(const_int 2)))
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(use (reg:SI 19))]
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"TARGET_SINGLE_STRINGOP || optimize_size"
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@ -10035,10 +10039,10 @@
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[(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
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(mem:QI (match_operand:SI 3 "register_operand" "1")))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_dup 0)
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(plus:SI (match_dup 2)
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(const_int 1)))
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(set (match_operand:SI 1 "register_operand" "=S")
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(plus:SI (match_dup 1)
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(plus:SI (match_dup 3)
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(const_int 1)))
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(use (reg:SI 19))]
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"TARGET_SINGLE_STRINGOP || optimize_size"
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@ -10047,21 +10051,18 @@
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(set_attr "memory" "both")
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(set_attr "mode" "QI")])
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;; It might seem that operands 3 & 4 could use predicate register_operand.
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;; But strength reduction might offset the MEM expression. So we let
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;; reload put the address into %edi & %esi.
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(define_insn "rep_movsi"
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[(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
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(use (match_operand:SI 5 "register_operand" "2"))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_operand:SI 3 "address_operand" "0")
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(ashift:SI (match_dup 5) (const_int 2))))
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(plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
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(const_int 2))
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(match_operand:SI 3 "register_operand" "0")))
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(set (match_operand:SI 1 "register_operand" "=S")
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(plus:SI (match_operand:SI 4 "address_operand" "1")
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(ashift:SI (match_dup 5) (const_int 2))))
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(plus:SI (ashift:SI (match_dup 5) (const_int 2))
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(match_operand:SI 4 "register_operand" "1")))
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(set (mem:BLK (match_dup 3))
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(mem:BLK (match_dup 4)))
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(use (match_dup 5))
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(use (reg:SI 19))]
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""
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"rep\;movsl|rep movsd"
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@ -10072,13 +10073,14 @@
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(define_insn "rep_movqi"
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[(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
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(use (match_operand:SI 5 "register_operand" "2"))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_operand:SI 3 "address_operand" "0") (match_dup 5)))
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(plus:SI (match_operand:SI 3 "register_operand" "0")
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(match_operand:SI 5 "register_operand" "2")))
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(set (match_operand:SI 1 "register_operand" "=S")
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(plus:SI (match_operand:SI 4 "address_operand" "1") (match_dup 5)))
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(plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
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(set (mem:BLK (match_dup 3))
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(mem:BLK (match_dup 4)))
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(use (match_dup 5))
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(use (reg:SI 19))]
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""
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"rep\;movsb|rep movsb"
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@ -10307,7 +10309,7 @@
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[(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
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(match_operand:SI 2 "register_operand" "a"))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_dup 0)
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(plus:SI (match_dup 1)
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(const_int 4)))
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(use (reg:SI 19))]
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"TARGET_SINGLE_STRINGOP || optimize_size"
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@ -10320,7 +10322,7 @@
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[(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
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(match_operand:HI 2 "register_operand" "a"))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_dup 0)
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(plus:SI (match_dup 1)
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(const_int 2)))
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(use (reg:SI 19))]
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"TARGET_SINGLE_STRINGOP || optimize_size"
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@ -10333,7 +10335,7 @@
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[(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
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(match_operand:QI 2 "register_operand" "a"))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_dup 0)
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(plus:SI (match_dup 1)
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(const_int 1)))
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(use (reg:SI 19))]
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"TARGET_SINGLE_STRINGOP || optimize_size"
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@ -10342,19 +10344,16 @@
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(set_attr "memory" "store")
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(set_attr "mode" "QI")])
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;; It might seem that operand 0 could use predicate register_operand.
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;; But strength reduction might offset the MEM expression. So we let
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;; reload put the address into %edi.
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(define_insn "rep_stossi"
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[(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
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(use (match_operand:SI 2 "register_operand" "a"))
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(use (match_operand:SI 4 "register_operand" "1"))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_operand:SI 3 "address_operand" "0")
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(ashift:SI (match_dup 3) (const_int 2))))
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(plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
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(const_int 2))
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(match_operand:SI 3 "register_operand" "0")))
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(set (mem:BLK (match_dup 3))
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(const_int 0))
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(use (match_operand:SI 2 "register_operand" "a"))
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(use (match_dup 4))
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(use (reg:SI 19))]
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""
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"rep\;stosl|rep stosd"
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@ -10365,12 +10364,13 @@
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(define_insn "rep_stosqi"
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[(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
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(use (match_operand:QI 2 "register_operand" "a"))
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(use (match_operand:SI 4 "register_operand" "1"))
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(set (match_operand:SI 0 "register_operand" "=D")
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(plus:SI (match_operand:SI 3 "address_operand" "0") (match_dup 3)))
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(plus:SI (match_operand:SI 3 "register_operand" "0")
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(match_operand:SI 4 "register_operand" "1")))
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(set (mem:BLK (match_dup 3))
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(const_int 0))
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(use (match_operand:QI 2 "register_operand" "a"))
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(use (match_dup 4))
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(use (reg:SI 19))]
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""
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"rep\;stosb|rep stosb"
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@ -10413,12 +10413,14 @@
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emit_move_insn (operands[0], const0_rtx);
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DONE;
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}
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emit_insn (gen_cmpstrsi_nz_1 (addr1, addr2, countreg, align));
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emit_insn (gen_cmpstrsi_nz_1 (addr1, addr2, countreg, align,
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addr1, addr2, countreg));
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}
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else
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{
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emit_insn (gen_cmpsi_1 (countreg, countreg));
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emit_insn (gen_cmpstrsi_1 (addr1, addr2, countreg, align));
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emit_insn (gen_cmpstrsi_1 (addr1, addr2, countreg, align,
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addr1, addr2, countreg));
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}
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outlow = gen_lowpart (QImode, out);
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@ -10448,21 +10450,17 @@
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;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is
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;; zero. Emit extra code to make sure that a zero-length compare is EQ.
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;;
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;; It might seem that operands 0 & 1 could use predicate register_operand.
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;; But strength reduction might offset the MEM expression. So we let
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;; reload put the address into %edi & %esi.
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(define_insn "cmpstrsi_nz_1"
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[(set (reg:CC 17)
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(compare:CC (mem:BLK (match_operand:SI 0 "address_operand" "S"))
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(mem:BLK (match_operand:SI 1 "address_operand" "D"))))
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(use (match_operand:SI 2 "register_operand" "c"))
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(compare:CC (mem:BLK (match_operand:SI 4 "register_operand" "0"))
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(mem:BLK (match_operand:SI 5 "register_operand" "1"))))
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(use (match_operand:SI 6 "register_operand" "2"))
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(use (match_operand:SI 3 "immediate_operand" "i"))
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(use (reg:SI 19))
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(clobber (match_dup 0))
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(clobber (match_dup 1))
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(clobber (match_dup 2))]
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(clobber (match_operand:SI 0 "register_operand" "=S"))
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(clobber (match_operand:SI 1 "register_operand" "=D"))
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(clobber (match_operand:SI 2 "register_operand" "=c"))]
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""
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"repz{\;| }cmpsb"
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[(set_attr "type" "str")
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@ -10473,17 +10471,17 @@
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(define_insn "cmpstrsi_1"
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[(set (reg:CC 17)
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(if_then_else:CC (ne (match_operand:SI 2 "register_operand" "c")
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(if_then_else:CC (ne (match_operand:SI 6 "register_operand" "2")
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(const_int 0))
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(compare:SI (mem:BLK (match_operand:SI 0 "address_operand" "S"))
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(mem:BLK (match_operand:SI 1 "address_operand" "D")))
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(compare:SI (mem:BLK (match_operand:SI 4 "register_operand" "0"))
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(mem:BLK (match_operand:SI 5 "register_operand" "1")))
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(const_int 0)))
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(use (match_operand:SI 3 "immediate_operand" "i"))
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(use (reg:CC 17))
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(use (reg:SI 19))
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(clobber (match_dup 0))
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(clobber (match_dup 1))
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(clobber (match_dup 2))]
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(clobber (match_operand:SI 0 "register_operand" "=S"))
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(clobber (match_operand:SI 1 "register_operand" "=D"))
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(clobber (match_operand:SI 2 "register_operand" "=c"))]
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""
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"repz{\;| }cmpsb"
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[(set_attr "type" "str")
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@ -10547,25 +10545,21 @@
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emit_insn (gen_cld ());
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emit_insn (gen_strlensi_1 (scratch1, scratch3, eoschar,
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align, constm1_rtx));
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align, constm1_rtx, scratch3));
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emit_insn (gen_one_cmplsi2 (scratch2, scratch1));
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emit_insn (gen_addsi3 (out, scratch2, constm1_rtx));
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}
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DONE;
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}")
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;; It might seem that operands 0 & 1 could use predicate register_operand.
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;; But strength reduction might offset the MEM expression. So we let
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;; reload put the address into %edi.
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(define_insn "strlensi_1"
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[(set (match_operand:SI 0 "register_operand" "=&c")
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(unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "D"))
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(unspec:SI [(mem:BLK (match_operand:SI 5 "register_operand" "1"))
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(match_operand:QI 2 "general_operand" "a")
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(match_operand:SI 3 "immediate_operand" "i")
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(match_operand:SI 4 "immediate_operand" "0")] 0))
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(use (reg:SI 19))
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(clobber (match_dup 1))
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(clobber (match_operand:SI 1 "register_operand" "=D"))
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(clobber (reg:CC 17))]
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""
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"repnz{\;| }scasb"
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@ -112,7 +112,7 @@ init_recog ()
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through this one. (The only exception is in combine.c.) */
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int
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recog_memoized (insn)
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recog_memoized_1 (insn)
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rtx insn;
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{
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if (INSN_CODE (insn) < 0)
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@ -1329,6 +1329,12 @@ extern void set_unique_reg_note PARAMS ((rtx, enum reg_note, rtx));
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/* Functions in rtlanal.c */
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/* Single set is implemented as macro for performance reasons. */
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#define single_set(I) (INSN_P (I) \
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? (GET_CODE (PATTERN (I)) == SET \
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? PATTERN (I) : single_set_1 (I)) \
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: NULL_RTX)
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extern int rtx_unstable_p PARAMS ((rtx));
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extern int rtx_varies_p PARAMS ((rtx));
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extern int rtx_addr_varies_p PARAMS ((rtx));
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@ -1347,7 +1353,7 @@ extern int no_jumps_between_p PARAMS ((rtx, rtx));
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extern int modified_in_p PARAMS ((rtx, rtx));
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extern int insn_dependent_p PARAMS ((rtx, rtx));
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extern int reg_set_p PARAMS ((rtx, rtx));
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extern rtx single_set PARAMS ((rtx));
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extern rtx single_set_1 PARAMS ((rtx));
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extern int multiple_sets PARAMS ((rtx));
|
||||
extern rtx find_last_value PARAMS ((rtx, rtx *, rtx, int));
|
||||
extern int refers_to_regno_p PARAMS ((unsigned int, unsigned int,
|
||||
|
||||
109
gcc/rtlanal.c
109
gcc/rtlanal.c
@ -842,46 +842,91 @@ insn_dependent_p_1 (x, pat, data)
|
||||
will not be used, which we ignore. */
|
||||
|
||||
rtx
|
||||
single_set (insn)
|
||||
single_set_1 (insn)
|
||||
rtx insn;
|
||||
{
|
||||
rtx set;
|
||||
rtx pat = PATTERN (insn);
|
||||
int i;
|
||||
|
||||
if (! INSN_P (insn))
|
||||
return 0;
|
||||
|
||||
if (GET_CODE (PATTERN (insn)) == SET)
|
||||
return PATTERN (insn);
|
||||
|
||||
else if (GET_CODE (PATTERN (insn)) == PARALLEL)
|
||||
if (GET_CODE (pat) == PARALLEL)
|
||||
{
|
||||
for (i = 0, set = 0; i < XVECLEN (PATTERN (insn), 0); i++)
|
||||
rtx x, sub;
|
||||
/* This part is is performance critical for targets that use a lot of
|
||||
parallels, such as i386. We want to accept as single set
|
||||
instructions even an instructions with multiple sets where only
|
||||
one has live result, but we attempt to delay this tests only for
|
||||
multiple set instructions to reduce amount of calls to
|
||||
find_reg_note and side_effects_p.
|
||||
|
||||
We expect the "common" instruction to be parallel with first SET
|
||||
followed by the clobbers. So first we get the set, then look
|
||||
if it is followed by USE or CLOBBER. If so, we just return expect
|
||||
no SETs after these. When SET is followed by another SET, we
|
||||
continue by the clomplex loop trought all members of PARALLEL.
|
||||
*/
|
||||
#ifdef ENABLE_CHECKING
|
||||
if (XVECLEN (pat, 0) < 2)
|
||||
abort ();
|
||||
#endif
|
||||
set = XVECEXP (pat, 0, 0);
|
||||
switch (GET_CODE (set))
|
||||
{
|
||||
rtx sub = XVECEXP (PATTERN (insn), 0, i);
|
||||
|
||||
switch (GET_CODE (sub))
|
||||
{
|
||||
case USE:
|
||||
case CLOBBER:
|
||||
break;
|
||||
|
||||
case SET:
|
||||
if (! find_reg_note (insn, REG_UNUSED, SET_DEST (sub))
|
||||
|| side_effects_p (sub))
|
||||
{
|
||||
if (set)
|
||||
return 0;
|
||||
else
|
||||
set = sub;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
#ifdef ENABLE_CHECKING
|
||||
case USE:
|
||||
case CLOBBER:
|
||||
/* Instruction should not consist only from USEs and CLOBBERS,
|
||||
since then gcc is allowed to remove it entirely. In case
|
||||
something else is present, it should be first in the pattern. */
|
||||
abort();
|
||||
#endif
|
||||
case SET:
|
||||
break;
|
||||
default:
|
||||
return NULL_RTX;
|
||||
}
|
||||
x = XVECEXP (pat, 0, 1);
|
||||
switch (GET_CODE (x))
|
||||
{
|
||||
case USE:
|
||||
case CLOBBER:
|
||||
#ifdef ENABLE_CHECKING
|
||||
/* The USEs and CLOBBERs should always come last in the pattern. */
|
||||
for (i = XVECLEN (pat, 0) - 1; i > 1; i--)
|
||||
if (GET_CODE (XVECEXP (pat, 0, i)) != USE
|
||||
&& GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
|
||||
abort();
|
||||
#endif
|
||||
return set;
|
||||
case SET:
|
||||
/* Multiple set insns - we are off the critical path now. */
|
||||
for (i = XVECLEN (pat, 0) - 1; i > 0; i--)
|
||||
{
|
||||
sub = XVECEXP (pat, 0, i);
|
||||
switch GET_CODE (sub)
|
||||
{
|
||||
case USE:
|
||||
case CLOBBER:
|
||||
break;
|
||||
|
||||
case SET:
|
||||
if (!set
|
||||
|| (find_reg_note (insn, REG_UNUSED, SET_DEST (set))
|
||||
&& side_effects_p (set)))
|
||||
set = sub;
|
||||
else if (! find_reg_note (insn, REG_UNUSED, SET_DEST (sub))
|
||||
|| side_effects_p (sub))
|
||||
return NULL_RTX;
|
||||
break;
|
||||
|
||||
default:
|
||||
return NULL_RTX;
|
||||
}
|
||||
}
|
||||
return set;
|
||||
default:
|
||||
return NULL_RTX;
|
||||
}
|
||||
return set;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user