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(dect): Rewrite pattern so that it can be combined.
From-SVN: r13307
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@ -222,10 +222,6 @@
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""
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"movt %0")
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;; ??? This combiner pattern does not work, because combine does not combine
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;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
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;; defined. Perhaps use a pseudo-reg for the T bit?
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(define_insn ""
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[(set (reg:SI 18)
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(eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
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@ -2108,17 +2104,10 @@
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;; Misc insns
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;; ------------------------------------------------------------------------
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;; ??? This combiner pattern does not work, because combine does not combine
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;; instructions that set a hard register when SMALL_REGISTER_CLASSES is
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;; defined. Perhaps use a pseudo-reg for the T bit?
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(define_insn "dect"
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[(parallel [(set (match_operand:SI 0 "arith_reg_operand" "=r")
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(plus:SI (match_dup 0)
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(const_int -1)))
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(set (reg:SI 18)
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(eq:SI (plus:SI (match_dup 0) (const_int -1))
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(const_int 0)))])]
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[(set (reg:SI 18)
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(eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
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(set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
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"TARGET_SH2"
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"dt %0")
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