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[PATCH][AArch64] Add BIC-imm and ORR-imm SIMD pattern
This patch adds the support for BIC (vector, immediate) and ORR (vector, immediate) SIMD patterns to the AArch64 backend. Committed on behalf of Sudi Das. Reviewed-by: Richard Earnshaw <Richard.Earnshaw@arm.com> Reviewed-by: James Greenhalgh <james.greenhalgh@arm.com> gcc/ * config/aarch64/aarch64-protos.h (enum simd_immediate_check): New check type for aarch64_simd_valid_immediate. (aarch64_output_simd_mov_immediate): Update prototype. (aarch64_simd_valid_immediate): Update prototype. * config/aarch64/aarch64-simd.md (orr<mode>3): modified pattern to add support for ORR-immediate. (and<mode>3): modified pattern to add support for BIC-immediate. * config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Function now checks for valid immediate for BIC and ORR based on new enum argument. (aarch64_output_simd_mov_immediate): Function now used to output BIC/ORR imm as well based on new enum argument. * config/aarch64/constraints.md (Do): New vector immediate constraint. (Db) : Likewise. * config/aarch64/predicates.md (aarch64_reg_or_orr_imm): New predicate. (aarch64_reg_or_bic_imm): Likewise. gcc/testsuite/ * gcc.target/aarch64/bic_imm_1.c: New test. * gcc.target/aarch64/orr_imm_1.c: Likewise. From-SVN: r253422
This commit is contained in:
Sudakshina Das
James Greenhalgh
parent
b419102c12
commit
ab6501d713
gcc
@ -1,3 +1,22 @@
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2017-10-04 Sudakshina Das <sudi.das@arm.com>
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* config/aarch64/aarch64-protos.h (enum simd_immediate_check): New
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check type for aarch64_simd_valid_immediate.
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(aarch64_output_simd_mov_immediate): Update prototype.
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(aarch64_simd_valid_immediate): Update prototype.
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* config/aarch64/aarch64-simd.md (orr<mode>3): modified pattern to add
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support for ORR-immediate.
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(and<mode>3): modified pattern to add support for BIC-immediate.
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* config/aarch64/aarch64.c (aarch64_simd_valid_immediate): Function
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now checks for valid immediate for BIC and ORR based on new enum
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argument.
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(aarch64_output_simd_mov_immediate): Function now used to output
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BIC/ORR imm as well based on new enum argument.
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* config/aarch64/constraints.md (Do): New vector immediate constraint.
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(Db) : Likewise.
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* config/aarch64/predicates.md (aarch64_reg_or_orr_imm): New predicate.
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(aarch64_reg_or_bic_imm): Likewise.
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2017-10-04 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* config/s390/vx-builtins.md ("vec_mergeh<mode>")
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@ -308,6 +308,16 @@ enum aarch64_parse_opt_result
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AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */
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};
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/* Enum to distinguish which type of check is to be done in
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aarch64_simd_valid_immediate. This is used as a bitmask where
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AARCH64_CHECK_MOV has both bits set. Thus AARCH64_CHECK_MOV will
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perform all checks. Adding new types would require changes accordingly. */
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enum simd_immediate_check {
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AARCH64_CHECK_ORR = 1 << 0,
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AARCH64_CHECK_BIC = 1 << 1,
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AARCH64_CHECK_MOV = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC
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};
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extern struct tune_params aarch64_tune_params;
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HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
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@ -345,7 +355,8 @@ bool aarch64_mov_operand_p (rtx, machine_mode);
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rtx aarch64_reverse_mask (machine_mode);
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bool aarch64_offset_7bit_signed_scaled_p (machine_mode, HOST_WIDE_INT);
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char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode);
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char *aarch64_output_simd_mov_immediate (rtx, machine_mode, unsigned);
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char *aarch64_output_simd_mov_immediate (rtx, machine_mode, unsigned,
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enum simd_immediate_check w = AARCH64_CHECK_MOV);
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bool aarch64_pad_reg_upward (machine_mode, const_tree, bool);
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bool aarch64_regno_ok_for_base_p (int, bool);
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bool aarch64_regno_ok_for_index_p (int, bool);
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@ -356,7 +367,8 @@ bool aarch64_simd_imm_zero_p (rtx, machine_mode);
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bool aarch64_simd_scalar_immediate_valid_for_move (rtx, scalar_int_mode);
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bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
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bool aarch64_simd_valid_immediate (rtx, machine_mode, bool,
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struct simd_immediate_info *);
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struct simd_immediate_info *,
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enum simd_immediate_check w = AARCH64_CHECK_MOV);
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bool aarch64_split_dimode_const_store (rtx, rtx);
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bool aarch64_symbolic_address_p (rtx);
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bool aarch64_uimm12_shift (HOST_WIDE_INT);
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@ -558,21 +558,45 @@
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[(set_attr "type" "neon_fp_abd_<stype><q>")]
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)
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;; For AND (vector, register) and BIC (vector, immediate)
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(define_insn "and<mode>3"
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(and:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w,w")
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(and:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w,0")
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(match_operand:VDQ_I 2 "aarch64_reg_or_bic_imm" "w,Db")))]
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"TARGET_SIMD"
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"and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
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{
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switch (which_alternative)
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{
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case 0:
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return "and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>";
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case 1:
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return aarch64_output_simd_mov_immediate (operands[2],
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<MODE>mode, GET_MODE_BITSIZE (<MODE>mode), AARCH64_CHECK_BIC);
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "neon_logic<q>")]
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)
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;; For ORR (vector, register) and ORR (vector, immediate)
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(define_insn "ior<mode>3"
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[(set (match_operand:VDQ_I 0 "register_operand" "=w")
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(ior:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
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(match_operand:VDQ_I 2 "register_operand" "w")))]
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[(set (match_operand:VDQ_I 0 "register_operand" "=w,w")
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(ior:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w,0")
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(match_operand:VDQ_I 2 "aarch64_reg_or_orr_imm" "w,Do")))]
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"TARGET_SIMD"
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"orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
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{
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switch (which_alternative)
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{
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case 0:
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return "orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>";
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case 1:
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return aarch64_output_simd_mov_immediate (operands[2],
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<MODE>mode, GET_MODE_BITSIZE (<MODE>mode), AARCH64_CHECK_ORR);
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "neon_logic<q>")]
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)
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@ -11483,7 +11483,8 @@ aarch64_vect_float_const_representable_p (rtx x)
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/* Return true for valid and false for invalid. */
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bool
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aarch64_simd_valid_immediate (rtx op, machine_mode mode, bool inverse,
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struct simd_immediate_info *info)
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struct simd_immediate_info *info,
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enum simd_immediate_check which)
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{
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#define CHECK(STRIDE, ELSIZE, CLASS, TEST, SHIFT, NEG) \
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matches = 1; \
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@ -11551,54 +11552,65 @@ aarch64_simd_valid_immediate (rtx op, machine_mode mode, bool inverse,
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do
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{
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CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0
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&& bytes[i + 2] == 0 && bytes[i + 3] == 0, 0, 0);
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if (which & AARCH64_CHECK_ORR)
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{
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CHECK (4, 32, 0, bytes[i] == bytes[0] && bytes[i + 1] == 0
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&& bytes[i + 2] == 0 && bytes[i + 3] == 0, 0, 0);
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CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1]
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&& bytes[i + 2] == 0 && bytes[i + 3] == 0, 8, 0);
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CHECK (4, 32, 1, bytes[i] == 0 && bytes[i + 1] == bytes[1]
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&& bytes[i + 2] == 0 && bytes[i + 3] == 0, 8, 0);
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CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0
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&& bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 16, 0);
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CHECK (4, 32, 2, bytes[i] == 0 && bytes[i + 1] == 0
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&& bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 16, 0);
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CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0
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&& bytes[i + 2] == 0 && bytes[i + 3] == bytes[3], 24, 0);
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CHECK (4, 32, 3, bytes[i] == 0 && bytes[i + 1] == 0
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&& bytes[i + 2] == 0 && bytes[i + 3] == bytes[3], 24, 0);
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CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0, 0, 0);
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CHECK (2, 16, 4, bytes[i] == bytes[0] && bytes[i + 1] == 0, 0, 0);
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CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1], 8, 0);
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CHECK (2, 16, 5, bytes[i] == 0 && bytes[i + 1] == bytes[1], 8, 0);
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}
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CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff
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&& bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 0, 1);
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if (which & AARCH64_CHECK_BIC)
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{
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CHECK (4, 32, 6, bytes[i] == bytes[0] && bytes[i + 1] == 0xff
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&& bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 0, 1);
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CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
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&& bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 8, 1);
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CHECK (4, 32, 7, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
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&& bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 8, 1);
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CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff
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&& bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 16, 1);
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CHECK (4, 32, 8, bytes[i] == 0xff && bytes[i + 1] == 0xff
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&& bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 16, 1);
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CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff
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&& bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3], 24, 1);
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CHECK (4, 32, 9, bytes[i] == 0xff && bytes[i + 1] == 0xff
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&& bytes[i + 2] == 0xff && bytes[i + 3] == bytes[3], 24, 1);
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CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff, 0, 1);
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CHECK (2, 16, 10, bytes[i] == bytes[0] && bytes[i + 1] == 0xff, 0, 1);
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CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1], 8, 1);
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CHECK (2, 16, 11, bytes[i] == 0xff && bytes[i + 1] == bytes[1], 8, 1);
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}
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CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
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&& bytes[i + 2] == 0 && bytes[i + 3] == 0, 8, 0);
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/* Shifting ones / 8-bit / 64-bit variants only checked
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for 'ALL' (MOVI/MVNI). */
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if (which == AARCH64_CHECK_MOV)
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{
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CHECK (4, 32, 12, bytes[i] == 0xff && bytes[i + 1] == bytes[1]
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&& bytes[i + 2] == 0 && bytes[i + 3] == 0, 8, 0);
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CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1]
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&& bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 8, 1);
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CHECK (4, 32, 13, bytes[i] == 0 && bytes[i + 1] == bytes[1]
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&& bytes[i + 2] == 0xff && bytes[i + 3] == 0xff, 8, 1);
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CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff
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&& bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 16, 0);
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CHECK (4, 32, 14, bytes[i] == 0xff && bytes[i + 1] == 0xff
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&& bytes[i + 2] == bytes[2] && bytes[i + 3] == 0, 16, 0);
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CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0
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&& bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 16, 1);
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CHECK (4, 32, 15, bytes[i] == 0 && bytes[i + 1] == 0
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&& bytes[i + 2] == bytes[2] && bytes[i + 3] == 0xff, 16, 1);
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CHECK (1, 8, 16, bytes[i] == bytes[0], 0, 0);
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CHECK (1, 8, 16, bytes[i] == bytes[0], 0, 0);
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CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff)
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&& bytes[i] == bytes[(i + 8) % idx], 0, 0);
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CHECK (1, 64, 17, (bytes[i] == 0 || bytes[i] == 0xff)
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&& bytes[i] == bytes[(i + 8) % idx], 0, 0);
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}
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}
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while (0);
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@ -13000,10 +13012,14 @@ aarch64_float_const_representable_p (rtx x)
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return (exponent >= 0 && exponent <= 7);
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}
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/* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
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immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
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output MOVI/MVNI, ORR or BIC immediate. */
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char*
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aarch64_output_simd_mov_immediate (rtx const_vector,
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machine_mode mode,
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unsigned width)
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unsigned width,
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enum simd_immediate_check which)
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{
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bool is_valid;
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static char templ[40];
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@ -13015,9 +13031,11 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
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struct simd_immediate_info info = { NULL_RTX, 0, 0, false, false };
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/* This will return true to show const_vector is legal for use as either
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a AdvSIMD MOVI instruction (or, implicitly, MVNI) immediate. It will
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also update INFO to show how the immediate should be generated. */
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is_valid = aarch64_simd_valid_immediate (const_vector, mode, false, &info);
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a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
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It will also update INFO to show how the immediate should be generated.
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WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
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is_valid = aarch64_simd_valid_immediate (const_vector, mode, false,
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&info, which);
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gcc_assert (is_valid);
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element_char = sizetochar (info.element_width);
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@ -13048,20 +13066,37 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
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}
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}
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mnemonic = info.mvn ? "mvni" : "movi";
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shift_op = info.msl ? "msl" : "lsl";
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gcc_assert (CONST_INT_P (info.value));
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if (lane_count == 1)
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snprintf (templ, sizeof (templ), "%s\t%%d0, " HOST_WIDE_INT_PRINT_HEX,
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mnemonic, UINTVAL (info.value));
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else if (info.shift)
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snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX
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", %s %d", mnemonic, lane_count, element_char,
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UINTVAL (info.value), shift_op, info.shift);
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if (which == AARCH64_CHECK_MOV)
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{
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mnemonic = info.mvn ? "mvni" : "movi";
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shift_op = info.msl ? "msl" : "lsl";
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if (lane_count == 1)
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snprintf (templ, sizeof (templ), "%s\t%%d0, " HOST_WIDE_INT_PRINT_HEX,
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mnemonic, UINTVAL (info.value));
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else if (info.shift)
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snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, "
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HOST_WIDE_INT_PRINT_HEX ", %s %d", mnemonic, lane_count,
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element_char, UINTVAL (info.value), shift_op, info.shift);
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else
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snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, "
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HOST_WIDE_INT_PRINT_HEX, mnemonic, lane_count,
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element_char, UINTVAL (info.value));
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}
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else
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snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, " HOST_WIDE_INT_PRINT_HEX,
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mnemonic, lane_count, element_char, UINTVAL (info.value));
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{
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/* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
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mnemonic = info.mvn ? "bic" : "orr";
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if (info.shift)
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snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, #"
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HOST_WIDE_INT_PRINT_DEC ", %s #%d", mnemonic, lane_count,
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element_char, UINTVAL (info.value), "lsl", info.shift);
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else
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snprintf (templ, sizeof (templ), "%s\t%%0.%d%c, #"
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HOST_WIDE_INT_PRINT_DEC, mnemonic, lane_count,
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element_char, UINTVAL (info.value));
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}
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return templ;
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}
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@ -190,6 +190,20 @@
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(and (match_code "const_double")
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(match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))")))
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(define_constraint "Do"
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"@internal
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A constraint that matches vector of immediates for orr."
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(and (match_code "const_vector")
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(match_test "aarch64_simd_valid_immediate (op, mode, false,
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NULL, AARCH64_CHECK_ORR)")))
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(define_constraint "Db"
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"@internal
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A constraint that matches vector of immediates for bic."
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(and (match_code "const_vector")
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(match_test "aarch64_simd_valid_immediate (op, mode, false,
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NULL, AARCH64_CHECK_BIC)")))
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(define_constraint "Dn"
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"@internal
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A constraint that matches vector of immediates."
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@ -69,6 +69,16 @@
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(ior (match_test "op == constm1_rtx")
|
||||
(match_test "op == const1_rtx"))))))
|
||||
|
||||
(define_predicate "aarch64_reg_or_orr_imm"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_test "aarch64_simd_valid_immediate (op, mode, false,
|
||||
NULL, AARCH64_CHECK_ORR)")))
|
||||
|
||||
(define_predicate "aarch64_reg_or_bic_imm"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_test "aarch64_simd_valid_immediate (op, mode, false,
|
||||
NULL, AARCH64_CHECK_BIC)")))
|
||||
|
||||
(define_predicate "aarch64_fp_compare_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(and (match_code "const_double")
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
2017-10-04 Sudakshina Das <sudi.das@arm.com>
|
||||
|
||||
* gcc.target/aarch64/bic_imm_1.c: New.
|
||||
* gcc.target/aarch64/orr_imm_1.c: Likewise.
|
||||
|
||||
2017-10-04 Nathan Sidwell <nathan@acm.org>
|
||||
|
||||
* g++.dg/abi/mangle41.C: Adjust diagnostics.
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user