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mips.md (ANYF, SCALARF): New mode macros.
* config/mips/mips.md (ANYF, SCALARF): New mode macros.
(loadx, storex, fmt, UNITMODE): New mode attributes.
(add{sf,df,v2sf}3, sub{sf,df,v2sf}3): Redefine using :ANYF.
(mul[sd]f3): Redefine using :SCALARF.
(*mul[sd]f3): Renamed from mul[sd]f3_internal. Use :SCALARF.
(*mul[sd]3_r4300): Likewise mul[sd]f3_r4300.
(*m{add,sub}{sf,df,v2sf}3): Name formerly unnamed patterns. Use :ANYF.
Check TARGET_FUSED_MADD for V2SF too.
(*nm{add,sub}{sf,df,v2sf}3{,_fastmath}): Likewise, except v2sf patterns
were already named.
(abs{sf,df,v2sf}3, neg{sf,df,v2sf}3): Redefine using :ANYF.
(*[sl][wd]xc1_[sd]i): Redefine using :ANYF.
From-SVN: r86720
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
74fc61d171
commit
aae0609ca9
@ -1,3 +1,18 @@
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2004-08-29 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.md (ANYF, SCALARF): New mode macros.
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(loadx, storex, fmt, UNITMODE): New mode attributes.
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(add{sf,df,v2sf}3, sub{sf,df,v2sf}3): Redefine using :ANYF.
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(mul[sd]f3): Redefine using :SCALARF.
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(*mul[sd]f3): Renamed from mul[sd]f3_internal. Use :SCALARF.
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(*mul[sd]3_r4300): Likewise mul[sd]f3_r4300.
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(*m{add,sub}{sf,df,v2sf}3): Name formerly unnamed patterns. Use :ANYF.
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Check TARGET_FUSED_MADD for V2SF too.
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(*nm{add,sub}{sf,df,v2sf}3{,_fastmath}): Likewise, except v2sf patterns
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were already named.
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(abs{sf,df,v2sf}3, neg{sf,df,v2sf}3): Redefine using :ANYF.
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(*[sl][wd]xc1_[sd]i): Redefine using :ANYF.
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2004-08-29 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.c (mips_init_builtins): Simplify. Only create
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@ -361,6 +361,16 @@
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;; conditional-move-type condition is needed.
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(define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
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;; This mode macro allows :ANYF to be used wherever a scalar or vector
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;; floating-point mode is allowed.
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(define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
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(DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
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(V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
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;; Like ANYF, but only applies to scalar modes.
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(define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
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(DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
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;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
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;; 32-bit version and "dsubu" in the 64-bit version.
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(define_mode_attr d [(SI "") (DI "d")])
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@ -369,6 +379,10 @@
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(define_mode_attr load [(SI "lw") (DI "ld")])
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(define_mode_attr store [(SI "sw") (DI "sd")])
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;; Similarly for MIPS IV indexed FPR loads and stores.
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(define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1")])
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(define_mode_attr storex [(SF "swxc1") (DF "sdxc1")])
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;; The unextended ranges of the MIPS16 addiu and daddiu instructions
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;; are different. Some forms of unextended addiu have an 8-bit immediate
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;; field but the equivalent daddiu has only a 5-bit field.
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@ -378,6 +392,13 @@
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;; a given mode.
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(define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
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;; This attribute gives the format suffix for floating-point operations.
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(define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
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;; This attribute gives the upper-case mode name for one unit of a
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;; floating-point mode.
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(define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
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;; This code macro allows all branch instructions to be generated from
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;; a single define_expand template.
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(define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
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@ -517,32 +538,14 @@
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;; ....................
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;;
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(define_insn "adddf3"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(plus:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"add.d\t%0,%1,%2"
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[(set_attr "type" "fadd")
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(set_attr "mode" "DF")])
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(define_insn "addsf3"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(plus:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT"
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"add.s\t%0,%1,%2"
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[(set_attr "type" "fadd")
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(set_attr "mode" "SF")])
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(define_insn "addv2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(plus:V2SF (match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f")))]
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"TARGET_PAIRED_SINGLE_FLOAT"
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"add.ps\t%0,%1,%2"
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(define_insn "add<mode>3"
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[(set (match_operand:ANYF 0 "register_operand" "=f")
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(plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
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(match_operand:ANYF 2 "register_operand" "f")))]
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""
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"add.<fmt>\t%0,%1,%2"
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[(set_attr "type" "fadd")
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(set_attr "mode" "SF")])
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(set_attr "mode" "<UNITMODE>")])
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(define_expand "add<mode>3"
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[(set (match_operand:GPR 0 "register_operand")
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@ -774,32 +777,14 @@
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;; ....................
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;;
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(define_insn "subdf3"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(minus:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"sub.d\t%0,%1,%2"
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[(set_attr "type" "fadd")
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(set_attr "mode" "DF")])
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(define_insn "subsf3"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(minus:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT"
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"sub.s\t%0,%1,%2"
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[(set_attr "type" "fadd")
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(set_attr "mode" "SF")])
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(define_insn "subv2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(minus:V2SF (match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f")))]
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"TARGET_PAIRED_SINGLE_FLOAT"
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"sub.ps\t%0,%1,%2"
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(define_insn "sub<mode>3"
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[(set (match_operand:ANYF 0 "register_operand" "=f")
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(minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
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(match_operand:ANYF 2 "register_operand" "f")))]
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""
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"sub.<fmt>\t%0,%1,%2"
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[(set_attr "type" "fadd")
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(set_attr "mode" "SF")])
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(set_attr "mode" "<UNITMODE>")])
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(define_insn "sub<mode>3"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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@ -828,63 +813,35 @@
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;; ....................
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;;
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(define_expand "muldf3"
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[(set (match_operand:DF 0 "register_operand")
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(mult:DF (match_operand:DF 1 "register_operand")
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(match_operand:DF 2 "register_operand")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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(define_expand "mul<mode>3"
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[(set (match_operand:SCALARF 0 "register_operand")
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(mult:SCALARF (match_operand:SCALARF 1 "register_operand")
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(match_operand:SCALARF 2 "register_operand")))]
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""
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"")
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(define_insn "muldf3_internal"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_4300_MUL_FIX"
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"mul.d\t%0,%1,%2"
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[(set_attr "type" "fmul")
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(set_attr "mode" "DF")])
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(define_insn "*mul<mode>3"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
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(match_operand:SCALARF 2 "register_operand" "f")))]
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"!TARGET_4300_MUL_FIX"
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"mul.<fmt>\t%0,%1,%2"
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[(set_attr "type" "fmul")
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(set_attr "mode" "<MODE>")])
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;; Early VR4300 silicon has a CPU bug where multiplies with certain
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;; operands may corrupt immediately following multiplies. This is a
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;; simple fix to insert NOPs.
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(define_insn "muldf3_r4300"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_4300_MUL_FIX"
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"mul.d\t%0,%1,%2\;nop"
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[(set_attr "type" "fmul")
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(set_attr "mode" "DF")
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(set_attr "length" "8")])
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(define_expand "mulsf3"
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[(set (match_operand:SF 0 "register_operand")
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(mult:SF (match_operand:SF 1 "register_operand")
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(match_operand:SF 2 "register_operand")))]
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"TARGET_HARD_FLOAT"
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"")
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(define_insn "mulsf3_internal"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(mult:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && !TARGET_4300_MUL_FIX"
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"mul.s\t%0,%1,%2"
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[(set_attr "type" "fmul")
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(set_attr "mode" "SF")])
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;; See muldf3_r4300.
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(define_insn "mulsf3_r4300"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(mult:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_4300_MUL_FIX"
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"mul.s\t%0,%1,%2\;nop"
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[(set_attr "type" "fmul")
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(set_attr "mode" "SF")
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(set_attr "length" "8")])
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(define_insn "*mul<mode>3_r4300"
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[(set (match_operand:SCALARF 0 "register_operand" "=f")
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(mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
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(match_operand:SCALARF 2 "register_operand" "f")))]
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"TARGET_4300_MUL_FIX"
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"mul.<fmt>\t%0,%1,%2\;nop"
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[(set_attr "type" "fmul")
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(set_attr "mode" "<MODE>")
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(set_attr "length" "8")])
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(define_insn "mulv2sf3"
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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@ -1672,197 +1629,73 @@
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;; Floating point multiply accumulate instructions.
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f"))
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(match_operand:DF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
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"madd.d\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "DF")])
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(define_insn ""
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[(set (match_operand:SF 0 "register_operand" "=f")
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(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f"))
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(match_operand:SF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
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"madd.s\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "SF")])
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(define_insn ""
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(plus:V2SF (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f"))
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(match_operand:V2SF 3 "register_operand" "f")))]
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"TARGET_PAIRED_SINGLE_FLOAT"
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"madd.ps\t%0,%3,%1,%2"
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(define_insn "*madd<mode>"
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[(set (match_operand:ANYF 0 "register_operand" "=f")
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(plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
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(match_operand:ANYF 2 "register_operand" "f"))
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(match_operand:ANYF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_FUSED_MADD"
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"madd.<fmt>\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "SF")])
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(set_attr "mode" "<UNITMODE>")])
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f"))
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(match_operand:DF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
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"msub.d\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "DF")])
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(define_insn ""
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[(set (match_operand:SF 0 "register_operand" "=f")
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(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f"))
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(match_operand:SF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
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"msub.s\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "SF")])
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(define_insn ""
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[(set (match_operand:V2SF 0 "register_operand" "=f")
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(minus:V2SF (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
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(match_operand:V2SF 2 "register_operand" "f"))
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(match_operand:V2SF 3 "register_operand" "f")))]
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"TARGET_PAIRED_SINGLE_FLOAT"
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"msub.ps\t%0,%3,%1,%2"
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(define_insn "*msub<mode>"
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[(set (match_operand:ANYF 0 "register_operand" "=f")
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(minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
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(match_operand:ANYF 2 "register_operand" "f"))
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(match_operand:ANYF 3 "register_operand" "f")))]
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"ISA_HAS_FP4 && TARGET_FUSED_MADD"
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"msub.<fmt>\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "SF")])
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(set_attr "mode" "<UNITMODE>")])
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f"))
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(match_operand:DF 3 "register_operand" "f"))))]
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
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&& TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (DFmode)"
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"nmadd.d\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "DF")])
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(minus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
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(match_operand:DF 2 "register_operand" "f"))
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(match_operand:DF 3 "register_operand" "f")))]
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
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&& TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (DFmode)"
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"nmadd.d\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "DF")])
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(define_insn ""
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[(set (match_operand:SF 0 "register_operand" "=f")
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(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f"))
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(match_operand:SF 3 "register_operand" "f"))))]
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"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
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&& HONOR_SIGNED_ZEROS (SFmode)"
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"nmadd.s\t%0,%3,%1,%2"
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[(set_attr "type" "fmadd")
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(set_attr "mode" "SF")])
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||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
|
||||
(match_operand:SF 2 "register_operand" "f"))
|
||||
(match_operand:SF 3 "register_operand" "f")))]
|
||||
"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
|
||||
&& !HONOR_SIGNED_ZEROS (SFmode)"
|
||||
"nmadd.s\t%0,%3,%1,%2"
|
||||
[(set_attr "type" "fmadd")
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "*nmaddv2sf"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=f")
|
||||
(neg:V2SF (plus:V2SF (mult:V2SF
|
||||
(match_operand:V2SF 1 "register_operand" "f")
|
||||
(match_operand:V2SF 2 "register_operand" "f"))
|
||||
(match_operand:V2SF 3 "register_operand" "f"))))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (V2SFmode)"
|
||||
"nmadd.ps\t%0,%3,%1,%2"
|
||||
(define_insn "*nmadd<mode>"
|
||||
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
||||
(neg:ANYF (plus:ANYF
|
||||
(mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
|
||||
(match_operand:ANYF 2 "register_operand" "f"))
|
||||
(match_operand:ANYF 3 "register_operand" "f"))))]
|
||||
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
|
||||
&& HONOR_SIGNED_ZEROS (<MODE>mode)"
|
||||
"nmadd.<fmt>\t%0,%3,%1,%2"
|
||||
[(set_attr "type" "fmadd")
|
||||
(set_attr "mode" "SF")])
|
||||
(set_attr "mode" "<UNITMODE>")])
|
||||
|
||||
(define_insn "*nmaddv2sf_fastmath"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=f")
|
||||
(minus:V2SF (mult:V2SF (neg:V2SF
|
||||
(match_operand:V2SF 1 "register_operand" "f"))
|
||||
(match_operand:V2SF 2 "register_operand" "f"))
|
||||
(match_operand:V2SF 3 "register_operand" "f")))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT && !HONOR_SIGNED_ZEROS (V2SFmode)"
|
||||
"nmadd.ps\t%0,%3,%1,%2"
|
||||
(define_insn "*nmadd<mode>_fastmath"
|
||||
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
||||
(minus:ANYF
|
||||
(mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
|
||||
(match_operand:ANYF 2 "register_operand" "f"))
|
||||
(match_operand:ANYF 3 "register_operand" "f")))]
|
||||
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
|
||||
&& !HONOR_SIGNED_ZEROS (<MODE>mode)"
|
||||
"nmadd.<fmt>\t%0,%3,%1,%2"
|
||||
[(set_attr "type" "fmadd")
|
||||
(set_attr "mode" "SF")])
|
||||
(set_attr "mode" "<UNITMODE>")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(neg:DF (minus:DF (mult:DF (match_operand:DF 2 "register_operand" "f")
|
||||
(match_operand:DF 3 "register_operand" "f"))
|
||||
(match_operand:DF 1 "register_operand" "f"))))]
|
||||
"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
|
||||
&& TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (DFmode)"
|
||||
"nmsub.d\t%0,%1,%2,%3"
|
||||
[(set_attr "type" "fmadd")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(minus:DF (match_operand:DF 1 "register_operand" "f")
|
||||
(mult:DF (match_operand:DF 2 "register_operand" "f")
|
||||
(match_operand:DF 3 "register_operand" "f"))))]
|
||||
"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
|
||||
&& TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (DFmode)"
|
||||
"nmsub.d\t%0,%1,%2,%3"
|
||||
[(set_attr "type" "fmadd")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(neg:SF (minus:SF (mult:SF (match_operand:SF 2 "register_operand" "f")
|
||||
(match_operand:SF 3 "register_operand" "f"))
|
||||
(match_operand:SF 1 "register_operand" "f"))))]
|
||||
"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
|
||||
&& HONOR_SIGNED_ZEROS (SFmode)"
|
||||
"nmsub.s\t%0,%1,%2,%3"
|
||||
[(set_attr "type" "fmadd")
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(minus:SF (match_operand:SF 1 "register_operand" "f")
|
||||
(mult:SF (match_operand:SF 2 "register_operand" "f")
|
||||
(match_operand:SF 3 "register_operand" "f"))))]
|
||||
"ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD
|
||||
&& !HONOR_SIGNED_ZEROS (SFmode)"
|
||||
"nmsub.s\t%0,%1,%2,%3"
|
||||
[(set_attr "type" "fmadd")
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "*nmsubv2sf"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=f")
|
||||
(neg:V2SF (minus:V2SF
|
||||
(mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
|
||||
(match_operand:V2SF 2 "register_operand" "f"))
|
||||
(match_operand:V2SF 3 "register_operand" "f"))))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (V2SFmode)"
|
||||
"nmsub.ps\t%0,%3,%1,%2"
|
||||
(define_insn "*nmsub<mode>"
|
||||
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
||||
(neg:ANYF (minus:ANYF
|
||||
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
|
||||
(match_operand:ANYF 3 "register_operand" "f"))
|
||||
(match_operand:ANYF 1 "register_operand" "f"))))]
|
||||
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
|
||||
&& HONOR_SIGNED_ZEROS (<MODE>mode)"
|
||||
"nmsub.<fmt>\t%0,%1,%2,%3"
|
||||
[(set_attr "type" "fmadd")
|
||||
(set_attr "mode" "SF")])
|
||||
(set_attr "mode" "<UNITMODE>")])
|
||||
|
||||
(define_insn "*nmsubv2sf_fastmath"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=f")
|
||||
(minus:V2SF (match_operand:V2SF 1 "register_operand" "f")
|
||||
(mult:V2SF (match_operand:V2SF 2 "register_operand" "f")
|
||||
(match_operand:V2SF 3 "register_operand" "f"))))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT && !HONOR_SIGNED_ZEROS (V2SFmode)"
|
||||
"nmsub.ps\t%0,%1,%2,%3"
|
||||
(define_insn "*nmsub<mode>_fastmath"
|
||||
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
||||
(minus:ANYF
|
||||
(match_operand:ANYF 1 "register_operand" "f")
|
||||
(mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
|
||||
(match_operand:ANYF 3 "register_operand" "f"))))]
|
||||
"ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
|
||||
&& !HONOR_SIGNED_ZEROS (<MODE>mode)"
|
||||
"nmsub.<fmt>\t%0,%1,%2,%3"
|
||||
[(set_attr "type" "fmadd")
|
||||
(set_attr "mode" "SF")])
|
||||
(set_attr "mode" "<UNITMODE>")])
|
||||
|
||||
;;
|
||||
;; ....................
|
||||
@ -2171,29 +2004,13 @@
|
||||
(set_attr "mode" "<MODE>")
|
||||
(set_attr "length" "12")])
|
||||
|
||||
(define_insn "absdf2"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(abs:DF (match_operand:DF 1 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"abs.d\t%0,%1"
|
||||
[(set_attr "type" "fabs")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
(define_insn "abssf2"
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(abs:SF (match_operand:SF 1 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT"
|
||||
"abs.s\t%0,%1"
|
||||
[(set_attr "type" "fabs")
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "absv2sf2"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=f")
|
||||
(abs:V2SF (match_operand:V2SF 1 "register_operand" "f")))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT"
|
||||
"abs.ps\t%0,%1"
|
||||
(define_insn "abs<mode>2"
|
||||
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
||||
(abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
|
||||
""
|
||||
"abs.<fmt>\t%0,%1"
|
||||
[(set_attr "type" "fabs")
|
||||
(set_attr "mode" "SF")])
|
||||
(set_attr "mode" "<UNITMODE>")])
|
||||
|
||||
;;
|
||||
;; ....................
|
||||
@ -2278,29 +2095,13 @@ beq\t%2,%.,1b\;\
|
||||
[(set_attr "type" "arith")
|
||||
(set_attr "mode" "DI")])
|
||||
|
||||
(define_insn "negdf2"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(neg:DF (match_operand:DF 1 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"neg.d\t%0,%1"
|
||||
[(set_attr "type" "fneg")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
(define_insn "negsf2"
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(neg:SF (match_operand:SF 1 "register_operand" "f")))]
|
||||
"TARGET_HARD_FLOAT"
|
||||
"neg.s\t%0,%1"
|
||||
[(set_attr "type" "fneg")
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "negv2sf2"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=f")
|
||||
(neg:V2SF (match_operand:V2SF 1 "register_operand" "f")))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT"
|
||||
"neg.ps\t%0,%1"
|
||||
(define_insn "neg<mode>2"
|
||||
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
||||
(neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
|
||||
""
|
||||
"neg.<fmt>\t%0,%1"
|
||||
[(set_attr "type" "fneg")
|
||||
(set_attr "mode" "SF")])
|
||||
(set_attr "mode" "<UNITMODE>")])
|
||||
|
||||
(define_insn "one_cmpl<mode>2"
|
||||
[(set (match_operand:GPR 0 "register_operand" "=d")
|
||||
@ -3900,81 +3701,23 @@ beq\t%2,%.,1b\;\
|
||||
;; these instructions can only be used to load and store floating
|
||||
;; point registers, that would probably cause trouble in reload.
|
||||
|
||||
(define_insn "*lwxc1_<mode>"
|
||||
[(set (match_operand:SF 0 "register_operand" "=f")
|
||||
(mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
|
||||
(match_operand:P 2 "register_operand" "d"))))]
|
||||
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
|
||||
"lwxc1\t%0,%1(%2)"
|
||||
(define_insn "*<ANYF:loadx>_<P:mode>"
|
||||
[(set (match_operand:ANYF 0 "register_operand" "=f")
|
||||
(mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
|
||||
(match_operand:P 2 "register_operand" "d"))))]
|
||||
"ISA_HAS_FP4"
|
||||
"<ANYF:loadx>\t%0,%1(%2)"
|
||||
[(set_attr "type" "fpidxload")
|
||||
(set_attr "mode" "SF")])
|
||||
(set_attr "mode" "<ANYF:UNITMODE>")])
|
||||
|
||||
(define_insn "*ldxc1_<mode>"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f")
|
||||
(mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
|
||||
(match_operand:P 2 "register_operand" "d"))))]
|
||||
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"ldxc1\t%0,%1(%2)"
|
||||
[(set_attr "type" "fpidxload")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
(define_insn "*ldxc1_v2sf_si"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=f")
|
||||
(mem:V2SF (plus:SI (match_operand:SI 1 "register_operand" "d")
|
||||
(match_operand:SI 2 "register_operand" "d"))))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT"
|
||||
"ldxc1\t%0,%1(%2)"
|
||||
[(set_attr "type" "fpidxload")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn "*ldxc1_v2sf_di"
|
||||
[(set (match_operand:V2SF 0 "register_operand" "=f")
|
||||
(mem:V2SF (plus:DI (match_operand:DI 1 "register_operand" "d")
|
||||
(match_operand:DI 2 "register_operand" "d"))))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT"
|
||||
"ldxc1\t%0,%1(%2)"
|
||||
[(set_attr "type" "fpidxload")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn "*swxc1_<mode>"
|
||||
[(set (mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
|
||||
(match_operand:P 2 "register_operand" "d")))
|
||||
(match_operand:SF 0 "register_operand" "f"))]
|
||||
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
|
||||
"swxc1\t%0,%1(%2)"
|
||||
(define_insn "*<ANYF:storex>_<P:mode>"
|
||||
[(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
|
||||
(match_operand:P 2 "register_operand" "d")))
|
||||
(match_operand:ANYF 0 "register_operand" "f"))]
|
||||
"ISA_HAS_FP4"
|
||||
"<ANYF:storex>\t%0,%1(%2)"
|
||||
[(set_attr "type" "fpidxstore")
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "*sdxc1_<mode>"
|
||||
[(set (mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
|
||||
(match_operand:P 2 "register_operand" "d")))
|
||||
(match_operand:DF 0 "register_operand" "f"))]
|
||||
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
|
||||
"sdxc1\t%0,%1(%2)"
|
||||
[(set_attr "type" "fpidxstore")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
(define_insn "*sdxc1_v2sf_si"
|
||||
[(set (mem:V2SF (plus:SI (match_operand:SI 1 "register_operand" "d")
|
||||
(match_operand:SI 2 "register_operand" "d")))
|
||||
(match_operand:V2SF 0 "register_operand" "f"))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT"
|
||||
"sdxc1\t%0,%1(%2)"
|
||||
[(set_attr "type" "fpidxstore")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn "*sdxc1_v2sf_di"
|
||||
[(set (mem:V2SF (plus:DI (match_operand:DI 1 "register_operand" "d")
|
||||
(match_operand:DI 2 "register_operand" "d")))
|
||||
(match_operand:V2SF 0 "register_operand" "f"))]
|
||||
"TARGET_PAIRED_SINGLE_FLOAT"
|
||||
"sdxc1\t%0,%1(%2)"
|
||||
[(set_attr "type" "fpidxstore")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4")])
|
||||
(set_attr "mode" "<ANYF:UNITMODE>")])
|
||||
|
||||
;; 16-bit Integer moves
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user