mirror of
git://gcc.gnu.org/git/gcc.git
synced 2025-03-15 22:51:38 +08:00
Delete cycle display scheduling hook.
2002-05-03 David S. Miller <davem@redhat.com> Delete cycle display scheduling hook. * config/ia64/ia64.c (ia64_cycle_display, TARGET_SCHED_CYCLE_DISPLAY, ia64_emit_insn_before): Delete. (ia64_sched_reorder2): Don't check for CODE_FOR_cycle_display and use emit_insn_before instead of ia64_emit_insn_before. * config/ia64/ia64.md (unspec usage): Delete cycle display. (cycle_display): Delete insn pattern. * config/sparc/sparc.md (unspec usage): Delete cycle display. (cycle_display): Delete insn pattern. * config/sparc/sparc.c (sparc_cycle_display, TARGET_SCHED_CYCLE_DISPLAY): Delete. * doc/md.texi (cycle_display): Don't mention. * doc/tm.texi (TARGET_SCHED_CYCLE_DISPLAY): Likewise. From-SVN: r53134
This commit is contained in:
David S. Miller
David S. Miller
parent
b37c26149f
commit
aaaed75228
@ -1,3 +1,19 @@
|
||||
2002-05-03 David S. Miller <davem@redhat.com>
|
||||
|
||||
Delete cycle display scheduling hook.
|
||||
* config/ia64/ia64.c (ia64_cycle_display,
|
||||
TARGET_SCHED_CYCLE_DISPLAY, ia64_emit_insn_before): Delete.
|
||||
(ia64_sched_reorder2): Don't check for CODE_FOR_cycle_display
|
||||
and use emit_insn_before instead of ia64_emit_insn_before.
|
||||
* config/ia64/ia64.md (unspec usage): Delete cycle display.
|
||||
(cycle_display): Delete insn pattern.
|
||||
* config/sparc/sparc.md (unspec usage): Delete cycle display.
|
||||
(cycle_display): Delete insn pattern.
|
||||
* config/sparc/sparc.c (sparc_cycle_display,
|
||||
TARGET_SCHED_CYCLE_DISPLAY): Delete.
|
||||
* doc/md.texi (cycle_display): Don't mention.
|
||||
* doc/tm.texi (TARGET_SCHED_CYCLE_DISPLAY): Likewise.
|
||||
|
||||
2002-05-03 Richard Henderson <rth@redhat.com>
|
||||
|
||||
* recog.c (store_data_bypass_p, if_test_bypass_p): New.
|
||||
|
||||
@ -152,7 +152,6 @@ static int ia64_internal_sched_reorder PARAMS ((FILE *, int, rtx *,
|
||||
static int ia64_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
|
||||
static int ia64_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
|
||||
static int ia64_variable_issue PARAMS ((FILE *, int, rtx, int));
|
||||
static rtx ia64_cycle_display PARAMS ((int, rtx));
|
||||
|
||||
|
||||
/* Table of valid machine attributes. */
|
||||
@ -211,8 +210,6 @@ static const struct attribute_spec ia64_attribute_table[] =
|
||||
#define TARGET_SCHED_REORDER ia64_sched_reorder
|
||||
#undef TARGET_SCHED_REORDER2
|
||||
#define TARGET_SCHED_REORDER2 ia64_sched_reorder2
|
||||
#undef TARGET_SCHED_CYCLE_DISPLAY
|
||||
#define TARGET_SCHED_CYCLE_DISPLAY ia64_cycle_display
|
||||
|
||||
struct gcc_target targetm = TARGET_INITIALIZER;
|
||||
|
||||
@ -5162,7 +5159,6 @@ int ia64_final_schedule = 0;
|
||||
static int itanium_split_issue PARAMS ((const struct ia64_packet *, int));
|
||||
static rtx ia64_single_set PARAMS ((rtx));
|
||||
static int insn_matches_slot PARAMS ((const struct ia64_packet *, enum attr_type, int, rtx));
|
||||
static void ia64_emit_insn_before PARAMS ((rtx, rtx));
|
||||
static void maybe_rotate PARAMS ((FILE *));
|
||||
static void finish_last_head PARAMS ((FILE *, int));
|
||||
static void rotate_one_bundle PARAMS ((FILE *));
|
||||
@ -5485,21 +5481,6 @@ insn_matches_slot (p, itype, slot, insn)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Like emit_insn_before, but skip cycle_display insns. This makes the
|
||||
assembly output a bit prettier. */
|
||||
|
||||
static void
|
||||
ia64_emit_insn_before (insn, before)
|
||||
rtx insn, before;
|
||||
{
|
||||
rtx prev = PREV_INSN (before);
|
||||
if (prev && GET_CODE (prev) == INSN
|
||||
&& GET_CODE (PATTERN (prev)) == UNSPEC
|
||||
&& XINT (PATTERN (prev), 1) == 23)
|
||||
before = prev;
|
||||
emit_insn_before (insn, before);
|
||||
}
|
||||
|
||||
/* When rotating a bundle out of the issue window, insert a bundle selector
|
||||
insn in front of it. DUMP is the scheduling dump file or NULL. START
|
||||
is either 0 or 3, depending on whether we want to emit a bundle selector
|
||||
@ -5531,7 +5512,7 @@ finish_last_head (dump, start)
|
||||
fprintf (dump, "// Emitting template before %d: %s\n",
|
||||
INSN_UID (insn), b->name);
|
||||
|
||||
ia64_emit_insn_before (gen_bundle_selector (GEN_INT (bundle_type)), insn);
|
||||
emit_insn_before (gen_bundle_selector (GEN_INT (bundle_type)), insn);
|
||||
}
|
||||
|
||||
/* We can't schedule more insns this cycle. Fix up the scheduling state
|
||||
@ -6391,9 +6372,8 @@ ia64_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
|
||||
abort ();
|
||||
insn_code = recog_memoized (stop);
|
||||
|
||||
/* Ignore cycle displays and .pred.rel.mutex. */
|
||||
if (insn_code == CODE_FOR_cycle_display
|
||||
|| insn_code == CODE_FOR_pred_rel_mutex
|
||||
/* Ignore .pred.rel.mutex. */
|
||||
if (insn_code == CODE_FOR_pred_rel_mutex
|
||||
|| insn_code == CODE_FOR_prologue_use)
|
||||
continue;
|
||||
|
||||
@ -6490,7 +6470,7 @@ ia64_variable_issue (dump, sched_verbose, insn, can_issue_more)
|
||||
int t = sched_data.first_slot;
|
||||
if (t == 0)
|
||||
t = 3;
|
||||
ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (t)), insn);
|
||||
emit_insn_before (gen_insn_group_barrier (GEN_INT (t)), insn);
|
||||
init_insn_group_barriers ();
|
||||
sched_data.last_was_stop = 0;
|
||||
}
|
||||
@ -6547,17 +6527,6 @@ ia64_sched_finish (dump, sched_verbose)
|
||||
free (sched_types);
|
||||
free (sched_ready);
|
||||
}
|
||||
|
||||
static rtx
|
||||
ia64_cycle_display (clock, last)
|
||||
int clock;
|
||||
rtx last;
|
||||
{
|
||||
if (ia64_final_schedule)
|
||||
return emit_insn_after (gen_cycle_display (GEN_INT (clock)), last);
|
||||
else
|
||||
return last;
|
||||
}
|
||||
|
||||
/* Emit pseudo-ops for the assembler to describe predicate relations.
|
||||
At present this assumes that we only consider predicate pairs to
|
||||
|
||||
@ -65,7 +65,6 @@
|
||||
;; 20 bsp_value
|
||||
;; 21 flushrs
|
||||
;; 22 bundle selector
|
||||
;; 23 cycle display
|
||||
;; 24 addp4
|
||||
;; 25 prologue_use
|
||||
;;
|
||||
@ -5012,13 +5011,6 @@
|
||||
""
|
||||
[(set_attr "itanium_class" "nop_x")])
|
||||
|
||||
(define_insn "cycle_display"
|
||||
[(unspec [(match_operand 0 "const_int_operand" "")] 23)]
|
||||
""
|
||||
"// cycle %0"
|
||||
[(set_attr "itanium_class" "ignore")
|
||||
(set_attr "predicable" "no")])
|
||||
|
||||
(define_insn "bundle_selector"
|
||||
[(unspec [(match_operand 0 "const_int_operand" "")] 22)]
|
||||
""
|
||||
|
||||
@ -167,7 +167,6 @@ static int sparc_issue_rate PARAMS ((void));
|
||||
static void sparc_sched_init PARAMS ((FILE *, int, int));
|
||||
static int sparc_use_dfa_pipeline_interface PARAMS ((void));
|
||||
static int sparc_use_sched_lookahead PARAMS ((void));
|
||||
static rtx sparc_cycle_display PARAMS ((int, rtx));
|
||||
|
||||
static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *));
|
||||
static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *));
|
||||
@ -233,8 +232,6 @@ enum processor_type sparc_cpu;
|
||||
#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
|
||||
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
|
||||
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
|
||||
#undef TARGET_SCHED_CYCLE_DISPLAY
|
||||
#define TARGET_SCHED_CYCLE_DISPLAY sparc_cycle_display
|
||||
|
||||
struct gcc_target targetm = TARGET_INITIALIZER;
|
||||
|
||||
@ -7690,17 +7687,6 @@ sparc_use_sched_lookahead ()
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rtx
|
||||
sparc_cycle_display (clock, last)
|
||||
int clock;
|
||||
rtx last;
|
||||
{
|
||||
if (reload_completed)
|
||||
return emit_insn_after (gen_cycle_display (GEN_INT (clock)), last);
|
||||
else
|
||||
return last;
|
||||
}
|
||||
|
||||
static int
|
||||
sparc_issue_rate ()
|
||||
{
|
||||
|
||||
@ -44,7 +44,6 @@
|
||||
;; 16 embmedany_textlo
|
||||
;; 18 sethm
|
||||
;; 19 setlo
|
||||
;; 20 cycle_display
|
||||
;;
|
||||
;; UNSPEC_VOLATILE: 0 blockage
|
||||
;; 1 flush_register_windows
|
||||
@ -9316,9 +9315,3 @@
|
||||
"TARGET_V9"
|
||||
"t%C0\\t%%xcc, %1"
|
||||
[(set_attr "type" "misc")])
|
||||
|
||||
(define_insn "cycle_display"
|
||||
[(unspec [(match_operand 0 "const_int_operand" "")] 20)]
|
||||
""
|
||||
"! cycle %0"
|
||||
[(set_attr "length" "0")])
|
||||
|
||||
@ -3200,14 +3200,6 @@ respectively, a low or moderate degree of temporal locality.
|
||||
Targets that do not support write prefetches or locality hints can ignore
|
||||
the values of operands 1 and 2.
|
||||
|
||||
@cindex @code{cycle_display} instruction pattern
|
||||
@item @samp{cycle_display}
|
||||
|
||||
This pattern, if present, will be emitted by the instruction scheduler at
|
||||
the beginning of each new clock cycle. This can be used for annotating the
|
||||
assembler output with cycle counts. Operand 0 is a @code{const_int} that
|
||||
holds the clock cycle.
|
||||
|
||||
@end table
|
||||
|
||||
@node Pattern Ordering
|
||||
|
||||
@ -5498,14 +5498,6 @@ to. @var{verbose} is the verbose level provided by
|
||||
@option{-fsched-verbose-@var{n}}.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} rtx TARGET_SCHED_CYCLE_DISPLAY (int @var{clock}, rtx @var{last})
|
||||
This hook is called in verbose mode only, at the beginning of each pass
|
||||
over a basic block. It should insert an insn into the chain after
|
||||
@var{last}, which has no effect, but records the value @var{clock} in
|
||||
RTL dumps and assembly output. Define this hook only if you need this
|
||||
level of detail about what the scheduler is doing.
|
||||
@end deftypefn
|
||||
|
||||
@deftypefn {Target Hook} int TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE (void)
|
||||
This hook is called many times during insn scheduling. If the hook
|
||||
returns nonzero, the automaton based pipeline description is used for
|
||||
|
||||
@ -2019,10 +2019,6 @@ schedule_block (b, rgn_n_insns)
|
||||
list. */
|
||||
queue_to_ready (&ready);
|
||||
|
||||
if (sched_verbose && targetm.sched.cycle_display)
|
||||
last_scheduled_insn
|
||||
= (*targetm.sched.cycle_display) (clock_var, last_scheduled_insn);
|
||||
|
||||
if (ready.n_ready == 0)
|
||||
abort ();
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user