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aarch64: Use RTL builtins for [su]mull_high_lane[q] intrinsics
Rewrite [su]mull_high_lane[q] Neon intrinsics to use RTL builtins rather than inline assembly code, allowing for better scheduling and optimization. gcc/ChangeLog: 2021-02-03 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add [su]mull_hi_lane[q] builtin generator macros. * config/aarch64/aarch64-simd.md (aarch64_<su>mull_hi_lane<mode>_insn): Define. (aarch64_<su>mull_hi_lane<mode>): Define. (aarch64_<su>mull_hi_laneq<mode>_insn): Define. (aarch64_<su>mull_hi_laneq<mode>): Define. * config/aarch64/arm_neon.h (vmull_high_lane_s16): Use RTL builtin instead of inline asm. (vmull_high_lane_s32): Likewise. (vmull_high_lane_u16): Likewise. (vmull_high_lane_u32): Likewise. (vmull_high_laneq_s16): Likewise. (vmull_high_laneq_s32): Likewise. (vmull_high_laneq_u16): Likewise. (vmull_high_laneq_u32): Liekwise.
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Jonathan Wright
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1d6228454c
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@ -303,6 +303,11 @@
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BUILTIN_VQ_HSI (BINOP, smull_hi_n, 0, NONE)
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BUILTIN_VQ_HSI (BINOPU, umull_hi_n, 0, NONE)
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BUILTIN_VQ_HSI (TERNOP_LANE, smull_hi_lane, 0, NONE)
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BUILTIN_VQ_HSI (TERNOP_LANE, smull_hi_laneq, 0, NONE)
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BUILTIN_VQ_HSI (TERNOPU_LANE, umull_hi_lane, 0, NONE)
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BUILTIN_VQ_HSI (TERNOPU_LANE, umull_hi_laneq, 0, NONE)
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BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_lane_, 0, NONE)
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BUILTIN_VD_HSI (QUADOP_LANE, vec_smlal_lane_, 0, NONE)
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BUILTIN_VD_HSI (TERNOP_LANE, vec_smult_laneq_, 0, NONE)
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@ -2253,6 +2253,70 @@
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[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
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)
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(define_insn "aarch64_<su>mull_hi_lane<mode>_insn"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(mult:<VWIDE>
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQ_HSI 1 "register_operand" "w")
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(match_operand:VQ_HSI 2 "vect_par_cnst_hi_half" "")))
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(ANY_EXTEND:<VWIDE> (vec_duplicate:<VHALF>
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(vec_select:<VEL>
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(match_operand:<VCOND> 3 "register_operand" "<vwx>")
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(parallel [(match_operand:SI 4 "immediate_operand" "i")]))))))]
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"TARGET_SIMD"
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{
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operands[4] = aarch64_endian_lane_rtx (<VCOND>mode, INTVAL (operands[4]));
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return "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %3.<Vetype>[%4]";
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}
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[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
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)
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(define_expand "aarch64_<su>mull_hi_lane<mode>"
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[(match_operand:<VWIDE> 0 "register_operand")
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(ANY_EXTEND:<VWIDE>(match_operand:VQ_HSI 1 "register_operand"))
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(match_operand:<VCOND> 2 "register_operand")
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(match_operand:SI 3 "immediate_operand")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_<su>mull_hi_lane<mode>_insn (operands[0],
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operands[1], p, operands[2], operands[3]));
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DONE;
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}
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)
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(define_insn "aarch64_<su>mull_hi_laneq<mode>_insn"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(mult:<VWIDE>
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(ANY_EXTEND:<VWIDE> (vec_select:<VHALF>
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(match_operand:VQ_HSI 1 "register_operand" "w")
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(match_operand:VQ_HSI 2 "vect_par_cnst_hi_half" "")))
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(ANY_EXTEND:<VWIDE> (vec_duplicate:<VHALF>
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(vec_select:<VEL>
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(match_operand:<VCONQ> 3 "register_operand" "<vwx>")
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(parallel [(match_operand:SI 4 "immediate_operand" "i")]))))))]
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"TARGET_SIMD"
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{
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operands[4] = aarch64_endian_lane_rtx (<VCONQ>mode, INTVAL (operands[4]));
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return "<su>mull2\\t%0.<Vwtype>, %1.<Vtype>, %3.<Vetype>[%4]";
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}
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[(set_attr "type" "neon_mul_<Vetype>_scalar_long")]
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)
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(define_expand "aarch64_<su>mull_hi_laneq<mode>"
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[(match_operand:<VWIDE> 0 "register_operand")
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(ANY_EXTEND:<VWIDE>(match_operand:VQ_HSI 1 "register_operand"))
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(match_operand:<VCONQ> 2 "register_operand")
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(match_operand:SI 3 "immediate_operand")]
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"TARGET_SIMD"
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{
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rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, true);
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emit_insn (gen_aarch64_<su>mull_hi_laneq<mode>_insn (operands[0],
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operands[1], p, operands[2], operands[3]));
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DONE;
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}
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)
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(define_insn "aarch64_<su>mull_n<mode>"
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[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
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(mult:<VWIDE>
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@ -8167,109 +8167,62 @@ vshrn_n_u64 (uint64x2_t __a, const int __b)
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{
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return (uint32x2_t)__builtin_aarch64_shrnv2di ((int64x2_t)__a, __b);
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}
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#define vmull_high_lane_s16(a, b, c) \
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__extension__ \
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({ \
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int16x4_t b_ = (b); \
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int16x8_t a_ = (a); \
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int32x4_t result; \
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__asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]" \
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: "=w"(result) \
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: "w"(a_), "x"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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#define vmull_high_lane_s32(a, b, c) \
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__extension__ \
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({ \
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int32x2_t b_ = (b); \
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int32x4_t a_ = (a); \
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int64x2_t result; \
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__asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]" \
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: "=w"(result) \
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: "w"(a_), "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmull_high_lane_s16 (int16x8_t __a, int16x4_t __v, const int __lane)
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{
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return __builtin_aarch64_smull_hi_lanev8hi (__a, __v, __lane);
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}
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#define vmull_high_lane_u16(a, b, c) \
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__extension__ \
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({ \
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uint16x4_t b_ = (b); \
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uint16x8_t a_ = (a); \
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uint32x4_t result; \
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__asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]" \
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: "=w"(result) \
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: "w"(a_), "x"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline int64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmull_high_lane_s32 (int32x4_t __a, int32x2_t __v, const int __lane)
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{
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return __builtin_aarch64_smull_hi_lanev4si (__a, __v, __lane);
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}
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#define vmull_high_lane_u32(a, b, c) \
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__extension__ \
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({ \
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uint32x2_t b_ = (b); \
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uint32x4_t a_ = (a); \
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uint64x2_t result; \
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__asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]" \
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: "=w"(result) \
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: "w"(a_), "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmull_high_lane_u16 (uint16x8_t __a, uint16x4_t __v, const int __lane)
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{
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return __builtin_aarch64_umull_hi_lanev8hi_uuus (__a, __v, __lane);
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}
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#define vmull_high_laneq_s16(a, b, c) \
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__extension__ \
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({ \
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int16x8_t b_ = (b); \
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int16x8_t a_ = (a); \
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int32x4_t result; \
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__asm__ ("smull2 %0.4s, %1.8h, %2.h[%3]" \
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: "=w"(result) \
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: "w"(a_), "x"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline uint64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmull_high_lane_u32 (uint32x4_t __a, uint32x2_t __v, const int __lane)
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{
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return __builtin_aarch64_umull_hi_lanev4si_uuus (__a, __v, __lane);
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}
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#define vmull_high_laneq_s32(a, b, c) \
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__extension__ \
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({ \
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int32x4_t b_ = (b); \
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int32x4_t a_ = (a); \
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int64x2_t result; \
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__asm__ ("smull2 %0.2d, %1.4s, %2.s[%3]" \
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: "=w"(result) \
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: "w"(a_), "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmull_high_laneq_s16 (int16x8_t __a, int16x8_t __v, const int __lane)
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{
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return __builtin_aarch64_smull_hi_laneqv8hi (__a, __v, __lane);
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}
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#define vmull_high_laneq_u16(a, b, c) \
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__extension__ \
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({ \
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uint16x8_t b_ = (b); \
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uint16x8_t a_ = (a); \
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uint32x4_t result; \
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__asm__ ("umull2 %0.4s, %1.8h, %2.h[%3]" \
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: "=w"(result) \
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: "w"(a_), "x"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline int64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmull_high_laneq_s32 (int32x4_t __a, int32x4_t __v, const int __lane)
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{
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return __builtin_aarch64_smull_hi_laneqv4si (__a, __v, __lane);
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}
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#define vmull_high_laneq_u32(a, b, c) \
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__extension__ \
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({ \
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uint32x4_t b_ = (b); \
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uint32x4_t a_ = (a); \
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uint64x2_t result; \
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__asm__ ("umull2 %0.2d, %1.4s, %2.s[%3]" \
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: "=w"(result) \
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: "w"(a_), "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmull_high_laneq_u16 (uint16x8_t __a, uint16x8_t __v, const int __lane)
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{
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return __builtin_aarch64_umull_hi_laneqv8hi_uuus (__a, __v, __lane);
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}
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__extension__ extern __inline uint64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmull_high_laneq_u32 (uint32x4_t __a, uint32x4_t __v, const int __lane)
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{
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return __builtin_aarch64_umull_hi_laneqv4si_uuus (__a, __v, __lane);
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}
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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