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[ARM/AArch64][testsuite] Add vmla_n and vmls_n tests.
2015-01-26 Christophe Lyon <christophe.lyon@linaro.org> * gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc: New file. * gcc.target/aarch64/advsimd-intrinsics/vmla_n.c: New file. * gcc.target/aarch64/advsimd-intrinsics/vmls_n.c: New file. From-SVN: r220118
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Christophe Lyon
Christophe Lyon
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2015-01-26 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/aarch64/advsimd-intrinsics/vmlX_n.inc: New file.
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* gcc.target/aarch64/advsimd-intrinsics/vmla_n.c: New file.
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* gcc.target/aarch64/advsimd-intrinsics/vmls_n.c: New file.
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2015-01-26 Christophe Lyon <christophe.lyon@linaro.org>
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* gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file.
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#define FNNAME1(NAME) exec_ ## NAME
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#define FNNAME(NAME) FNNAME1(NAME)
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void FNNAME (INSN_NAME) (void)
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{
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#define DECL_VMLX_N(VAR) \
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DECL_VARIABLE(VAR, int, 16, 4); \
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DECL_VARIABLE(VAR, int, 32, 2); \
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DECL_VARIABLE(VAR, uint, 16, 4); \
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DECL_VARIABLE(VAR, uint, 32, 2); \
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DECL_VARIABLE(VAR, float, 32, 2); \
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DECL_VARIABLE(VAR, int, 16, 8); \
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DECL_VARIABLE(VAR, int, 32, 4); \
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DECL_VARIABLE(VAR, uint, 16, 8); \
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DECL_VARIABLE(VAR, float, 32, 4); \
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DECL_VARIABLE(VAR, uint, 32, 4)
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/* vector_res = vmlx_n(vector, vector2, val),
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then store the result. */
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#define TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V) \
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VECT_VAR(vector_res, T1, W, N) = \
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INSN##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \
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VECT_VAR(vector2, T1, W, N), \
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V); \
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vst1##Q##_##T2##W(VECT_VAR(result, T1, W, N), \
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VECT_VAR(vector_res, T1, W, N))
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#define TEST_VMLX_N(INSN, Q, T1, T2, W, N, V) \
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TEST_VMLX_N1(INSN, Q, T1, T2, W, N, V)
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DECL_VMLX_N(vector);
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DECL_VMLX_N(vector2);
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DECL_VMLX_N(vector_res);
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clean_results ();
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VLOAD(vector, buffer, , int, s, 16, 4);
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VLOAD(vector, buffer, , int, s, 32, 2);
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VLOAD(vector, buffer, , uint, u, 16, 4);
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VLOAD(vector, buffer, , uint, u, 32, 2);
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VLOAD(vector, buffer, , float, f, 32, 2);
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VLOAD(vector, buffer, q, int, s, 16, 8);
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VLOAD(vector, buffer, q, int, s, 32, 4);
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VLOAD(vector, buffer, q, uint, u, 16, 8);
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VLOAD(vector, buffer, q, uint, u, 32, 4);
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VLOAD(vector, buffer, q, float, f, 32, 4);
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VDUP(vector2, , int, s, 16, 4, 0x55);
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VDUP(vector2, , int, s, 32, 2, 0x55);
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VDUP(vector2, , uint, u, 16, 4, 0x55);
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VDUP(vector2, , uint, u, 32, 2, 0x55);
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VDUP(vector2, , float, f, 32, 2, 55.2f);
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VDUP(vector2, q, int, s, 16, 8, 0x55);
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VDUP(vector2, q, int, s, 32, 4, 0x55);
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VDUP(vector2, q, uint, u, 16, 8, 0x55);
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VDUP(vector2, q, uint, u, 32, 4, 0x55);
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VDUP(vector2, q, float, f, 32, 4, 55.9f);
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/* Choose multiplier arbitrarily. */
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TEST_VMLX_N(INSN_NAME, , int, s, 16, 4, 0x11);
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TEST_VMLX_N(INSN_NAME, , int, s, 32, 2, 0x22);
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TEST_VMLX_N(INSN_NAME, , uint, u, 16, 4, 0x33);
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TEST_VMLX_N(INSN_NAME, , uint, u, 32, 2, 0x44);
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TEST_VMLX_N(INSN_NAME, , float, f, 32, 2, 22.3f);
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TEST_VMLX_N(INSN_NAME, q, int, s, 16, 8, 0x55);
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TEST_VMLX_N(INSN_NAME, q, int, s, 32, 4, 0x66);
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TEST_VMLX_N(INSN_NAME, q, uint, u, 16, 8, 0x77);
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TEST_VMLX_N(INSN_NAME, q, uint, u, 32, 4, 0x88);
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TEST_VMLX_N(INSN_NAME, q, float, f, 32, 4, 66.7f);
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CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, "");
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CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, "");
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CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, "");
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CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, "");
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CHECK_FP(TEST_MSG, float, 32, 2, PRIx32, expected, "");
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CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, "");
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CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, "");
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CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, "");
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CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, "");
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CHECK_FP(TEST_MSG, float, 32, 4, PRIx32, expected, "");
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}
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int main (void)
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{
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FNNAME (INSN_NAME) ();
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return 0;
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}
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23
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
Normal file
23
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmla_n.c
Normal file
@ -0,0 +1,23 @@
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#include <arm_neon.h>
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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#define INSN_NAME vmla
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#define TEST_MSG "VMLA_N"
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/* Expected results. */
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VECT_VAR_DECL(expected,int,16,4) [] = { 0x595, 0x596, 0x597, 0x598 };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0xb3a, 0xb3b };
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VECT_VAR_DECL(expected,uint,16,4) [] = { 0x10df, 0x10e0, 0x10e1, 0x10e2 };
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VECT_VAR_DECL(expected,uint,32,2) [] = { 0x1684, 0x1685 };
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VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x4497deb8, 0x4497feb8 };
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VECT_VAR_DECL(expected,int,16,8) [] = { 0x1c29, 0x1c2a, 0x1c2b, 0x1c2c,
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0x1c2d, 0x1c2e, 0x1c2f, 0x1c30 };
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VECT_VAR_DECL(expected,int,32,4) [] = { 0x21ce, 0x21cf, 0x21d0, 0x21d1 };
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VECT_VAR_DECL(expected,uint,16,8) [] = { 0x2773, 0x2774, 0x2775, 0x2776,
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0x2777, 0x2778, 0x2779, 0x277a };
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VECT_VAR_DECL(expected,uint,32,4) [] = { 0x2d18, 0x2d19, 0x2d1a, 0x2d1b };
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x4568087b, 0x4568187b,
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0x4568287b, 0x4568387b };
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#include "vmlX_n.inc"
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25
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
Normal file
25
gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmls_n.c
Normal file
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#include <arm_neon.h>
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#include "arm-neon-ref.h"
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#include "compute-ref-data.h"
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#define INSN_NAME vmls
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#define TEST_MSG "VMLS_N"
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/* Expected results. */
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VECT_VAR_DECL(expected,int,16,4) [] = { 0xfa4b, 0xfa4c, 0xfa4d, 0xfa4e };
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VECT_VAR_DECL(expected,int,32,2) [] = { 0xfffff4a6, 0xfffff4a7 };
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VECT_VAR_DECL(expected,uint,16,4) [] = { 0xef01, 0xef02, 0xef03, 0xef04 };
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VECT_VAR_DECL(expected,uint,32,2) [] = { 0xffffe95c, 0xffffe95d };
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VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0xc49bdeb8, 0xc49bbeb8 };
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VECT_VAR_DECL(expected,int,16,8) [] = { 0xe3b7, 0xe3b8, 0xe3b9, 0xe3ba,
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0xe3bb, 0xe3bc, 0xe3bd, 0xe3be };
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VECT_VAR_DECL(expected,int,32,4) [] = { 0xffffde12, 0xffffde13,
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0xffffde14, 0xffffde15 };
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VECT_VAR_DECL(expected,uint,16,8) [] = { 0xd86d, 0xd86e, 0xd86f, 0xd870,
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0xd871, 0xd872, 0xd873, 0xd874 };
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VECT_VAR_DECL(expected,uint,32,4) [] = { 0xffffd2c8, 0xffffd2c9,
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0xffffd2ca, 0xffffd2cb };
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VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0xc56a087b, 0xc569f87b,
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0xc569e87b, 0xc569d87b };
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#include "vmlX_n.inc"
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