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[arm] Replace command-line option .def files with single definition file

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The files arm-cores.def, arm-fpus.def and arm-arches.def are parsed and
used in several places and the format is slightly awkward to maintain
as they must be parsable in C and by certain scripts.  Furthermore,
changes to the content that affects every entry is particularly awkward for
dealing with merges.

This patch replaces all three files with a single file that specifies all
the command-line related definitions in a new format that allows for better
checking for consistency as well as (hopefully) easier to merge changes.

The awk script used to parse it is relatively complicated, but should be
pretty portable.  It works by parsing in all the data and then operating
one of a number of possible sub-commands to generate the desired output.

The new method picked up one error.  The CPU descriptions referred to an
architecture ARMv5tej which was not supported by -march.  This has been
fixed by adding the relevant entry to the architecture list.

gcc:
	* config.gcc: Use new awk script to check CPU, FPU and architecture
	parameters for --with-... options.
	* config/arm/parsecpu.awk: New file
	* config/arm/arm-cpus.in: New file.
	* config/arm/arm-opts.h: Include arm-cpu.h instead of processing .def
	files.
	* config/arm/arm.c: Include arm-cpu-data.h instead of processing .def
	files.
	* config/arm/t-arm: Update dependency rules.
	* common/config/arm/arm-common.c: Include arm-cpu-cdata.h instead
	of processing .def files.
	* config/arm/genopt.sh: Deleted.
	* config/arm/gentune.sh: Deleted.
	* config/arm/arm-cores.def: Deleted.
	* config/arm/arm-arches.def: Deleted.
	* config/arm/arm-fpus.def: Deleted.
	* config/arm/arm-tune.md: Regenerated.
	* config/arm/arm-tables.opt: Regenerated.
	* config/arm/arm-cpu.h: New generated file.
	* config/arm/arm-cpu-data.h: New generated file.
	* config/arm/arm-cpu-cdata.h: New generated file.

Contrib:
	* gcc_update: Adjust touch list.

From-SVN: r244316
This commit is contained in:
Richard Earnshaw 2017-01-11 14:39:00 +00:00 committed by Richard Earnshaw
parent ca280d38f9
commit a92ffb3e94
20 changed files with 4702 additions and 604 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
contrib/ChangeLog
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@ -1,3 +1,7 @@
2017-01-11 Richard Earnshaw <rearnsha@arm.com>
* gcc_update: Adjust touch list for ARM.
2017-01-08 Gerald Pfeifer <gerald@pfeifer.com>
* download_ecj: Remove.

7
contrib/gcc_update
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@ -80,8 +80,11 @@ gcc/cstamp-h.in: gcc/configure.ac
gcc/config.in: gcc/cstamp-h.in
gcc/fixinc/fixincl.x: gcc/fixinc/fixincl.tpl gcc/fixinc/inclhack.def
gcc/config/aarch64/aarch64-tune.md: gcc/config/aarch64/aarch64-cores.def gcc/config/aarch64/gentune.sh
gcc/config/arm/arm-tune.md: gcc/config/arm/arm-cores.def gcc/config/arm/gentune.sh
gcc/config/arm/arm-tables.opt: gcc/config/arm/arm-arches.def gcc/config/arm/arm-cores.def gcc/config/arm/arm-fpus.def gcc/config/arm/genopt.sh
gcc/config/arm/arm-tune.md: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
gcc/config/arm/arm-tables.opt: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
gcc/config/arm/arm-cpu.h: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
gcc/config/arm/arm-cpu-data.h: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
gcc/config/arm/arm-cpu-cdata.h: gcc/config/arm/arm-cpus.in gcc/config/arm/parsecpu.awk
gcc/config/avr/avr-tables.opt: gcc/config/avr/avr-mcus.def gcc/config/avr/genopt.sh
gcc/config/avr/t-multilib: gcc/config/avr/avr-mcus.def gcc/config/avr/genmultilib.awk
gcc/config/c6x/c6x-tables.opt: gcc/config/c6x/c6x-isas.def gcc/config/c6x/genopt.sh

24
gcc/ChangeLog
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@ -1,3 +1,27 @@
2017-01-11 Richard Earnshaw <rearnsha@arm.com>
* config.gcc: Use new awk script to check CPU, FPU and architecture
parameters for --with-... options.
* config/arm/parsecpu.awk: New file
* config/arm/arm-cpus.in: New file.
* config/arm/arm-opts.h: Include arm-cpu.h instead of processing .def
files.
* config/arm/arm.c: Include arm-cpu-data.h instead of processing .def
files.
* config/arm/t-arm: Update dependency rules.
* common/config/arm/arm-common.c: Include arm-cpu-cdata.h instead
of processing .def files.
* config/arm/genopt.sh: Deleted.
* config/arm/gentune.sh: Deleted.
* config/arm/arm-cores.def: Deleted.
* config/arm/arm-arches.def: Deleted.
* config/arm/arm-fpus.def: Deleted.
* config/arm/arm-tune.md: Regenerated.
* config/arm/arm-tables.opt: Regenerated.
* config/arm/arm-cpu.h: New generated file.
* config/arm/arm-cpu-data.h: New generated file.
* config/arm/arm-cpu-cdata.h: New generated file.
2017-01-11 Maxim Ostapenko <m.ostapenko@samsung.com>
PR lto/79042

14
gcc/common/config/arm/arm-common.c
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@ -104,19 +104,7 @@ struct arm_arch_core_flag
const enum isa_feature isa_bits[isa_num_bits];
};
static const struct arm_arch_core_flag arm_arch_core_flags[] =
{
#undef ARM_CORE
#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
{NAME, {ISA isa_nobit}},
#include "config/arm/arm-cores.def"
#undef ARM_CORE
#undef ARM_ARCH
#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA) \
{NAME, {ISA isa_nobit}},
#include "config/arm/arm-arches.def"
#undef ARM_ARCH
};
#include "config/arm/arm-cpu-cdata.h"
/* Scan over a raw feature array BITS checking for BIT being present.
This is slower than the normal bitmask checks, but we would spend longer

63
gcc/config.gcc
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@ -3675,41 +3675,24 @@ case "${target}" in
arm*-*-*)
supported_defaults="arch cpu float tune fpu abi mode tls"
for which in cpu tune; do
# See if it matches any of the entries in arm-cores.def
for which in cpu tune arch; do
# See if it matches a supported value
eval "val=\$with_$which"
if [ x"$val" = x ] \
|| grep "^ARM_CORE(\"$val\"," \
${srcdir}/config/arm/arm-cores.def \
> /dev/null; then
# Ok
new_val=`grep "^ARM_CORE(\"$val\"," \
${srcdir}/config/arm/arm-cores.def | \
sed -e 's/^[^,]*,[ ]*//' | \
sed -e 's/,.*$//'`
if [ x"$val" != x ] ; then
eval "target_${which}_cname=$new_val"
echo "For $val real value is $new_val"
if [ x"$val" != x ]; then
cpu=`awk -f ${srcdir}/config/arm/parsecpu.awk \
-v cmd="chk$which $val" \
${srcdir}/config/arm/arm-cpus.in`
if [ "$cpu" = "error" ]; then
echo "Unknown target in --with-$which=$val" 1>&2
exit 1
else
new_val=$cpu
eval "target_${which}_cname=$new_val"
echo "For $val real value is $new_val"
fi
true
else
echo "Unknown CPU used in --with-$which=$val" 1>&2
exit 1
fi
done
# See if it matches any of the entries in arm-arches.def
if [ x"$with_arch" = x ] \
|| grep "^ARM_ARCH(\"$with_arch\"," \
${srcdir}/config/arm/arm-arches.def \
> /dev/null; then
# OK
true
else
echo "Unknown arch used in --with-arch=$with_arch" 1>&2
exit 1
fi
case "$with_float" in
"" \
| soft | hard | softfp)
@ -3721,16 +3704,16 @@ case "${target}" in
;;
esac
# see if it matches any of the entries in arm-fpus.def
if [ x"$with_fpu" = x ] \
|| grep "^ARM_FPU(\"$with_fpu\"," \
${srcdir}/config/arm/arm-fpus.def \
> /dev/null; then
# OK
true
else
echo "Unknown fpu used in --with-fpu=$with_fpu" 1>&2
exit 1
# see if --with-fpu matches any of the supported FPUs
if [ x"$with_fpu" != x ] ; then
fpu=`awk -f ${srcdir}/config/arm/parsecpu.awk \
-v cmd="chkfpu $with_fpu" \
${srcdir}/config/arm/arm-cpus.in`
if [ "$fpu" = "error"]
then
echo "Unknown target in --with-$which=$val" 1>&2
exit 1
fi
fi
case "$with_abi" in

67
gcc/config/arm/arm-arches.def
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@ -1,67 +0,0 @@
/* ARM CPU architectures.
Copyright (C) 1991-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Before using #include to read this file, define a macro:
ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA)
The NAME is the name of the architecture, represented as a string
constant. The CORE is the identifier for a core representative of
this architecture. ARCH is the architecture revision. ISA is the
detailed architectural capabilities of the core (see arm-isa.h).
genopt.sh assumes no whitespace up to the first "," in each entry. */
ARM_ARCH("armv2", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26))
ARM_ARCH("armv2a", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26))
ARM_ARCH("armv3", arm6, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26))
ARM_ARCH("armv3m", arm7m, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26))
ARM_ARCH("armv4", arm7tdmi, TF_CO_PROC, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26))
/* Strictly, isa_bit_mode26 is a permitted option for v4t, but there are no
implementations that support it, so we will leave it out for now. */
ARM_ARCH("armv4t", arm7tdmi, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t))
ARM_ARCH("armv5", arm10tdmi, TF_CO_PROC, 5, ISA_FEAT(ISA_ARMv5))
ARM_ARCH("armv5t", arm10tdmi, TF_CO_PROC, 5T, ISA_FEAT(ISA_ARMv5t))
ARM_ARCH("armv5e", arm1026ejs, TF_CO_PROC, 5E, ISA_FEAT(ISA_ARMv5e))
ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 5TE, ISA_FEAT(ISA_ARMv5te))
ARM_ARCH("armv6", arm1136js, TF_CO_PROC, 6, ISA_FEAT(ISA_ARMv6))
ARM_ARCH("armv6j", arm1136js, TF_CO_PROC, 6J, ISA_FEAT(ISA_ARMv6j))
ARM_ARCH("armv6k", mpcore, TF_CO_PROC, 6K, ISA_FEAT(ISA_ARMv6k))
ARM_ARCH("armv6z", arm1176jzs, TF_CO_PROC, 6Z, ISA_FEAT(ISA_ARMv6z))
ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 6KZ, ISA_FEAT(ISA_ARMv6kz))
ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 6KZ, ISA_FEAT(ISA_ARMv6kz))
ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 6T2, ISA_FEAT(ISA_ARMv6t2))
ARM_ARCH("armv6-m", cortexm1, 0, 6M, ISA_FEAT(ISA_ARMv6m))
ARM_ARCH("armv6s-m", cortexm1, 0, 6M, ISA_FEAT(ISA_ARMv6m))
ARM_ARCH("armv7", cortexa8, TF_CO_PROC, 7, ISA_FEAT(ISA_ARMv7))
ARM_ARCH("armv7-a", cortexa8, TF_CO_PROC, 7A, ISA_FEAT(ISA_ARMv7a))
ARM_ARCH("armv7ve", cortexa8, TF_CO_PROC, 7A, ISA_FEAT(ISA_ARMv7ve))
ARM_ARCH("armv7-r", cortexr4, TF_CO_PROC, 7R, ISA_FEAT(ISA_ARMv7r))
ARM_ARCH("armv7-m", cortexm3, TF_CO_PROC, 7M, ISA_FEAT(ISA_ARMv7m))
ARM_ARCH("armv7e-m", cortexm4, TF_CO_PROC, 7EM, ISA_FEAT(ISA_ARMv7em))
ARM_ARCH("armv8-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8a))
ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32))
ARM_ARCH("armv8.1-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_1a))
ARM_ARCH ("armv8.2-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_2a))
ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_2a) ISA_FEAT(isa_bit_fp16))
ARM_ARCH("armv8-m.base", cortexm23, 0, 8M_BASE, ISA_FEAT(ISA_ARMv8m_base))
ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main))
ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em))
ARM_ARCH("iwmmxt", iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt))
ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2))

188
gcc/config/arm/arm-cores.def
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@ -1,188 +0,0 @@
/* ARM CPU Cores
Copyright (C) 2003-2017 Free Software Foundation, Inc.
Written by CodeSourcery, LLC
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Before using #include to read this file, define a macro:
ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, ISA, COSTS)
The CORE_NAME is the name of the core, represented as a string constant.
The INTERNAL_IDENT is the name of the core represented as an identifier.
This must be unique for each entry in this table.
The TUNE_IDENT is the name of the core for which scheduling decisions
should be made, represented as an identifier.
TUNE_FLAGS is a set of flag bits that are used to affect tuning.
ARCH is the architecture revision implemented by the chip.
ISA is the detailed architectural capabilities of the core (see arm-isa.h).
COSTS is the name of the rtx_costs routine to use.
If you update this table, you must update the "tune" attribute in
arm.md.
Some tools assume no whitespace up to the first "," in each entry. */
/* V2/V2A Architecture Processors */
ARM_CORE("arm2", arm2, arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm250", arm250, arm250, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm3", arm3, arm3, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
/* V3 Architecture Processors */
ARM_CORE("arm6", arm6, arm6, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm60", arm60, arm60, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm600", arm600, arm600, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm610", arm610, arm610, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm620", arm620, arm620, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm7", arm7, arm7, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm7d", arm7d, arm7d, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm7di", arm7di, arm7di, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm70", arm70, arm70, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm700", arm700, arm700, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm700i", arm700i, arm700i, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm710", arm710, arm710, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm720", arm720, arm720, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm710c", arm710c, arm710c, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm7100", arm7100, arm7100, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
ARM_CORE("arm7500", arm7500, arm7500, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
/* Doesn't have an external co-proc, but does have embedded fpa (fpa no-longer supported). */
ARM_CORE("arm7500fe", arm7500fe, arm7500fe, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
/* V3M Architecture Processors */
/* arm7m doesn't exist on its own, but only with D, ("and", and I), but
those don't alter the code, so arm7m is sometimes used. */
ARM_CORE("arm7m", arm7m, arm7m, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
ARM_CORE("arm7dm", arm7dm, arm7dm, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
ARM_CORE("arm7dmi", arm7dmi, arm7dmi, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
/* V4 Architecture Processors */
ARM_CORE("arm8", arm8, arm8, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), fastmul)
ARM_CORE("arm810", arm810, arm810, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), fastmul)
ARM_CORE("strongarm", strongarm, strongarm, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
ARM_CORE("strongarm110", strongarm110, strongarm110, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
ARM_CORE("fa526", fa526, fa526, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4), fastmul)
ARM_CORE("fa626", fa626, fa626, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4), fastmul)
/* V4T Architecture Processors */
ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm710t", arm710t, arm710t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm720t", arm720t, arm720t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm740t", arm740t, arm740t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm9", arm9, arm9, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm920", arm920, arm920, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm920t", arm920t, arm920t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm922t", arm922t, arm922t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("arm940t", arm940t, arm940t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
ARM_CORE("ep9312", ep9312, ep9312, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
/* V5T Architecture Processors */
ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, TF_LDSCHED, 5T, ISA_FEAT(ISA_ARMv5t), fastmul)
ARM_CORE("arm1020t", arm1020t, arm1020t, TF_LDSCHED, 5T, ISA_FEAT(ISA_ARMv5t), fastmul)
/* V5TE Architecture Processors */
ARM_CORE("arm9e", arm9e, arm9e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
ARM_CORE("arm946e-s", arm946es, arm946es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
ARM_CORE("arm966e-s", arm966es, arm966es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
ARM_CORE("arm968e-s", arm968es, arm968es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
ARM_CORE("arm10e", arm10e, arm10e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), fastmul)
ARM_CORE("arm1020e", arm1020e, arm1020e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), fastmul)
ARM_CORE("arm1022e", arm1022e, arm1022e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), fastmul)
ARM_CORE("xscale", xscale, xscale, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale), xscale)
ARM_CORE("iwmmxt", iwmmxt, iwmmxt, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), xscale)
ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), xscale)
ARM_CORE("fa606te", fa606te, fa606te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
ARM_CORE("fa626te", fa626te, fa626te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
ARM_CORE("fmp626", fmp626, fmp626, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
ARM_CORE("fa726te", fa726te, fa726te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), fa726te)
/* V5TEJ Architecture Processors */
ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(ISA_ARMv5tej), 9e)
ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(ISA_ARMv5tej), 9e)
/* V6 Architecture Processors */
ARM_CORE("arm1136j-s", arm1136js, arm1136js, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j), 9e)
ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e)
ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz), 9e)
ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e)
ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k), 9e)
ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e)
ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2), v6t2)
ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), v6t2)
/* V6M Architecture Processors */
ARM_CORE("cortex-m1", cortexm1, cortexm1, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), v6m)
ARM_CORE("cortex-m0", cortexm0, cortexm0, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), v6m)
ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), v6m)
/* V6M Architecture Processors for small-multiply implementations. */
ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), v6m)
ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), v6m)
ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), v6m)
/* V7 Architecture Processors */
ARM_CORE("generic-armv7-a", genericv7a, genericv7a, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), cortex)
ARM_CORE("cortex-a5", cortexa5, cortexa5, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), cortex_a5)
ARM_CORE("cortex-a7", cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), cortex_a7)
ARM_CORE("cortex-a8", cortexa8, cortexa8, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), cortex_a8)
ARM_CORE("cortex-a9", cortexa9, cortexa9, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), cortex_a9)
ARM_CORE("cortex-a12", cortexa12, cortexa17, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), cortex_a12)
ARM_CORE("cortex-a15", cortexa15, cortexa15, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), cortex_a15)
ARM_CORE("cortex-a17", cortexa17, cortexa17, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), cortex_a12)
ARM_CORE("cortex-r4", cortexr4, cortexr4, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r), cortex)
ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r), cortex)
ARM_CORE("cortex-r5", cortexr5, cortexr5, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), cortex_m7)
ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em), v7m)
ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), v7m)
ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), marvell_pj4)
/* V7 big.LITTLE implementations */
ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), cortex_a15)
ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), cortex_a12)
/* V8 A-profile Architecture Processors */
ARM_CORE("cortex-a32", cortexa32, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a35)
ARM_CORE("cortex-a35", cortexa35, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a35)
ARM_CORE("cortex-a53", cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a53)
ARM_CORE("cortex-a57", cortexa57, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
ARM_CORE("cortex-a72", cortexa72, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
ARM_CORE("cortex-a73", cortexa73, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
ARM_CORE("exynos-m1", exynosm1, exynosm1, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), exynosm1)
ARM_CORE("falkor", falkor, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), qdf24xx)
ARM_CORE("qdf24xx", qdf24xx, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), qdf24xx)
ARM_CORE("xgene1", xgene1, xgene1, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a), xgene1)
/* V8 A-profile big.LITTLE implementations */
ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
/* V8 M-profile implementations. */
ARM_CORE("cortex-m23", cortexm23, cortexm23, TF_LDSCHED, 8M_BASE, ISA_FEAT(ISA_ARMv8m_base), v6m)
ARM_CORE("cortex-m33", cortexm33, cortexm33, TF_LDSCHED, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), v7m)

1058
gcc/config/arm/arm-cpu-cdata.h Normal file
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1652
gcc/config/arm/arm-cpu-data.h Normal file
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162
gcc/config/arm/arm-cpu.h Normal file
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@ -0,0 +1,162 @@
/* -*- buffer-read-only: t -*-
Generated automatically by parsecpu.awk from arm-cpus.in.
Do not edit.
Copyright (C) 2011-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 3,
or (at your option) any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public
License along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
enum processor_type
{
TARGET_CPU_arm2,
TARGET_CPU_arm250,
TARGET_CPU_arm3,
TARGET_CPU_arm6,
TARGET_CPU_arm60,
TARGET_CPU_arm600,
TARGET_CPU_arm610,
TARGET_CPU_arm620,
TARGET_CPU_arm7,
TARGET_CPU_arm7d,
TARGET_CPU_arm7di,
TARGET_CPU_arm70,
TARGET_CPU_arm700,
TARGET_CPU_arm700i,
TARGET_CPU_arm710,
TARGET_CPU_arm720,
TARGET_CPU_arm710c,
TARGET_CPU_arm7100,
TARGET_CPU_arm7500,
TARGET_CPU_arm7500fe,
TARGET_CPU_arm7m,
TARGET_CPU_arm7dm,
TARGET_CPU_arm7dmi,
TARGET_CPU_arm8,
TARGET_CPU_arm810,
TARGET_CPU_strongarm,
TARGET_CPU_strongarm110,
TARGET_CPU_strongarm1100,
TARGET_CPU_strongarm1110,
TARGET_CPU_fa526,
TARGET_CPU_fa626,
TARGET_CPU_arm7tdmi,
TARGET_CPU_arm7tdmis,
TARGET_CPU_arm710t,
TARGET_CPU_arm720t,
TARGET_CPU_arm740t,
TARGET_CPU_arm9,
TARGET_CPU_arm9tdmi,
TARGET_CPU_arm920,
TARGET_CPU_arm920t,
TARGET_CPU_arm922t,
TARGET_CPU_arm940t,
TARGET_CPU_ep9312,
TARGET_CPU_arm10tdmi,
TARGET_CPU_arm1020t,
TARGET_CPU_arm9e,
TARGET_CPU_arm946es,
TARGET_CPU_arm966es,
TARGET_CPU_arm968es,
TARGET_CPU_arm10e,
TARGET_CPU_arm1020e,
TARGET_CPU_arm1022e,
TARGET_CPU_xscale,
TARGET_CPU_iwmmxt,
TARGET_CPU_iwmmxt2,
TARGET_CPU_fa606te,
TARGET_CPU_fa626te,
TARGET_CPU_fmp626,
TARGET_CPU_fa726te,
TARGET_CPU_arm926ejs,
TARGET_CPU_arm1026ejs,
TARGET_CPU_arm1136js,
TARGET_CPU_arm1136jfs,
TARGET_CPU_arm1176jzs,
TARGET_CPU_arm1176jzfs,
TARGET_CPU_mpcorenovfp,
TARGET_CPU_mpcore,
TARGET_CPU_arm1156t2s,
TARGET_CPU_arm1156t2fs,
TARGET_CPU_cortexm1,
TARGET_CPU_cortexm0,
TARGET_CPU_cortexm0plus,
TARGET_CPU_cortexm1smallmultiply,
TARGET_CPU_cortexm0smallmultiply,
TARGET_CPU_cortexm0plussmallmultiply,
TARGET_CPU_genericv7a,
TARGET_CPU_cortexa5,
TARGET_CPU_cortexa7,
TARGET_CPU_cortexa8,
TARGET_CPU_cortexa9,
TARGET_CPU_cortexa12,
TARGET_CPU_cortexa15,
TARGET_CPU_cortexa17,
TARGET_CPU_cortexr4,
TARGET_CPU_cortexr4f,
TARGET_CPU_cortexr5,
TARGET_CPU_cortexr7,
TARGET_CPU_cortexr8,
TARGET_CPU_cortexm7,
TARGET_CPU_cortexm4,
TARGET_CPU_cortexm3,
TARGET_CPU_marvell_pj4,
TARGET_CPU_cortexa15cortexa7,
TARGET_CPU_cortexa17cortexa7,
TARGET_CPU_cortexa32,
TARGET_CPU_cortexa35,
TARGET_CPU_cortexa53,
TARGET_CPU_cortexa57,
TARGET_CPU_cortexa72,
TARGET_CPU_cortexa73,
TARGET_CPU_exynosm1,
TARGET_CPU_falkor,
TARGET_CPU_qdf24xx,
TARGET_CPU_xgene1,
TARGET_CPU_cortexa57cortexa53,
TARGET_CPU_cortexa72cortexa53,
TARGET_CPU_cortexa73cortexa35,
TARGET_CPU_cortexa73cortexa53,
TARGET_CPU_cortexm23,
TARGET_CPU_cortexm33,
TARGET_CPU_arm_none
};
enum fpu_type
{
TARGET_FPU_vfp,
TARGET_FPU_vfpv2,
TARGET_FPU_vfpv3,
TARGET_FPU_vfpv3_fp16,
TARGET_FPU_vfpv3_d16,
TARGET_FPU_vfpv3_d16_fp16,
TARGET_FPU_vfpv3xd,
TARGET_FPU_vfpv3xd_fp16,
TARGET_FPU_neon,
TARGET_FPU_neon_vfpv3,
TARGET_FPU_neon_fp16,
TARGET_FPU_vfpv4,
TARGET_FPU_neon_vfpv4,
TARGET_FPU_vfpv4_d16,
TARGET_FPU_fpv4_sp_d16,
TARGET_FPU_fpv5_sp_d16,
TARGET_FPU_fpv5_d16,
TARGET_FPU_fp_armv8,
TARGET_FPU_neon_fp_armv8,
TARGET_FPU_crypto_neon_fp_armv8,
TARGET_FPU_vfp3,
TARGET_FPU_auto
};

1182
gcc/config/arm/arm-cpus.in Normal file
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51
gcc/config/arm/arm-fpus.def
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@ -1,51 +0,0 @@
/* ARM FPU variants.
Copyright (C) 1991-2017 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* Before using #include to read this file, define a macro:
ARM_FPU(NAME, CNAME, ISA)
NAME is the publicly visible option name.
CNAME is a C-compatible variable name substring.
ISA is the list of feature bits that this FPU provides.
genopt.sh assumes no whitespace up to the first "," in each entry. */
ARM_FPU("vfp", vfp, ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
ARM_FPU("vfpv2", vfpv2, ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
ARM_FPU("vfpv3", vfpv3, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
ARM_FPU("vfpv3-fp16", vfpv3_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv))
ARM_FPU("vfpv3-d16", vfpv3_d16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL))
ARM_FPU("vfpv3-d16-fp16", vfpv3_d16_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv))
ARM_FPU("vfpv3xd", vfpv3xd, ISA_FEAT(ISA_VFPv3))
ARM_FPU("vfpv3xd-fp16", vfpv3xd_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv))
ARM_FPU("neon", neon, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
ARM_FPU("neon-vfpv3", neon_vfpv3, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
ARM_FPU("neon-fp16", neon_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv))
ARM_FPU("vfpv4", vfpv4, ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32))
ARM_FPU("neon-vfpv4", neon_vfpv4, ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON))
ARM_FPU("vfpv4-d16", vfpv4_d16, ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL))
ARM_FPU("fpv4-sp-d16", fpv4_sp_d16, ISA_FEAT(ISA_VFPv4))
ARM_FPU("fpv5-sp-d16", fpv5_sp_d16, ISA_FEAT(ISA_FPv5))
ARM_FPU("fpv5-d16", fpv5_d16, ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL))
ARM_FPU("fp-armv8", fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32))
ARM_FPU("neon-fp-armv8", neon_fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON))
ARM_FPU("crypto-neon-fp-armv8", crypto_neon_fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO))
/* Compatibility aliases. */
ARM_FPU("vfp3", vfp3, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))

23
gcc/config/arm/arm-opts.h
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@ -27,28 +27,7 @@
#include "arm-flags.h"
#include "arm-isa.h"
/* The various ARM cores. */
enum processor_type
{
#undef ARM_CORE
#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
TARGET_CPU_##INTERNAL_IDENT,
#include "arm-cores.def"
#undef ARM_CORE
/* Used to indicate that no processor has been specified. */
TARGET_CPU_arm_none
};
/* The various ARM FPUs. */
enum fpu_type
{
#undef ARM_FPU
#define ARM_FPU(NAME, CNAME, ISA) TARGET_FPU_##CNAME,
#include "arm-fpus.def"
TARGET_FPU_auto
#undef ARM_FPU
};
#include "arm-cpu.h"
/* Which __fp16 format to use.
The enumeration values correspond to the numbering for the

85
gcc/config/arm/arm-tables.opt
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@ -1,23 +1,23 @@
; -*- buffer-read-only: t -*-
; Generated automatically by genopt.sh from arm-cores.def, arm-arches.def
; and arm-fpus.def.
; Generated automatically by parsecpu.awk from arm-cpus.in.
; Do not edit.
; Copyright (C) 2011-2017 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; GCC is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as
; published by the Free Software Foundation; either version 3,
; or (at your option) any later version.
; GCC is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
; You should have received a copy of the GNU General Public
; License along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
Enum
@ -389,79 +389,82 @@ EnumValue
Enum(arm_arch) String(armv5te) Value(9)
EnumValue
Enum(arm_arch) String(armv6) Value(10)
Enum(arm_arch) String(armv5tej) Value(10)
EnumValue
Enum(arm_arch) String(armv6j) Value(11)
Enum(arm_arch) String(armv6) Value(11)
EnumValue
Enum(arm_arch) String(armv6k) Value(12)
Enum(arm_arch) String(armv6j) Value(12)
EnumValue
Enum(arm_arch) String(armv6z) Value(13)
Enum(arm_arch) String(armv6k) Value(13)
EnumValue
Enum(arm_arch) String(armv6kz) Value(14)
Enum(arm_arch) String(armv6z) Value(14)
EnumValue
Enum(arm_arch) String(armv6zk) Value(15)
Enum(arm_arch) String(armv6kz) Value(15)
EnumValue
Enum(arm_arch) String(armv6t2) Value(16)
Enum(arm_arch) String(armv6zk) Value(16)
EnumValue
Enum(arm_arch) String(armv6-m) Value(17)
Enum(arm_arch) String(armv6t2) Value(17)
EnumValue
Enum(arm_arch) String(armv6s-m) Value(18)
Enum(arm_arch) String(armv6-m) Value(18)
EnumValue
Enum(arm_arch) String(armv7) Value(19)
Enum(arm_arch) String(armv6s-m) Value(19)
EnumValue
Enum(arm_arch) String(armv7-a) Value(20)
Enum(arm_arch) String(armv7) Value(20)
EnumValue
Enum(arm_arch) String(armv7ve) Value(21)
Enum(arm_arch) String(armv7-a) Value(21)
EnumValue
Enum(arm_arch) String(armv7-r) Value(22)
Enum(arm_arch) String(armv7ve) Value(22)
EnumValue
Enum(arm_arch) String(armv7-m) Value(23)
Enum(arm_arch) String(armv7-r) Value(23)
EnumValue
Enum(arm_arch) String(armv7e-m) Value(24)
Enum(arm_arch) String(armv7-m) Value(24)
EnumValue
Enum(arm_arch) String(armv8-a) Value(25)
Enum(arm_arch) String(armv7e-m) Value(25)
EnumValue
Enum(arm_arch) String(armv8-a+crc) Value(26)
Enum(arm_arch) String(armv8-a) Value(26)
EnumValue
Enum(arm_arch) String(armv8.1-a) Value(27)
Enum(arm_arch) String(armv8-a+crc) Value(27)
EnumValue
Enum(arm_arch) String(armv8.2-a) Value(28)
Enum(arm_arch) String(armv8.1-a) Value(28)
EnumValue
Enum(arm_arch) String(armv8.2-a+fp16) Value(29)
Enum(arm_arch) String(armv8.2-a) Value(29)
EnumValue
Enum(arm_arch) String(armv8-m.base) Value(30)
Enum(arm_arch) String(armv8.2-a+fp16) Value(30)
EnumValue
Enum(arm_arch) String(armv8-m.main) Value(31)
Enum(arm_arch) String(armv8-m.base) Value(31)
EnumValue
Enum(arm_arch) String(armv8-m.main+dsp) Value(32)
Enum(arm_arch) String(armv8-m.main) Value(32)
EnumValue
Enum(arm_arch) String(iwmmxt) Value(33)
Enum(arm_arch) String(armv8-m.main+dsp) Value(33)
EnumValue
Enum(arm_arch) String(iwmmxt2) Value(34)
Enum(arm_arch) String(iwmmxt) Value(34)
EnumValue
Enum(arm_arch) String(iwmmxt2) Value(35)
Enum
Name(arm_fpu) Type(enum fpu_type)

24
gcc/config/arm/arm-tune.md
View File

@ -1,5 +1,25 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from arm-cores.def
; -*- buffer-read-only: t -*-
; Generated automatically by parsecpu.awk from arm-cpus.in.
; Do not edit.
; Copyright (C) 2011-2017 Free Software Foundation, Inc.
; This file is part of GCC.
; GCC is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as
; published by the Free Software Foundation; either version 3,
; or (at your option) any later version.
; GCC is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
; You should have received a copy of the GNU General Public
; License along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
(define_attr "tune"
"arm2,arm250,arm3,
arm6,arm60,arm600,

40
gcc/config/arm/arm.c
View File

@ -2293,33 +2293,8 @@ const struct tune_params arm_fa726te_tune =
tune_params::SCHED_AUTOPREF_OFF
};
/* Not all of these give usefully different compilation alternatives,
but there is no simple way of generalizing them. */
static const struct processors all_cores[] =
{
/* ARM Cores */
#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
{NAME, TARGET_CPU_##IDENT, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
{ISA isa_nobit}, &arm_##COSTS##_tune},
#include "arm-cores.def"
#undef ARM_CORE
{NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
};
static const struct processors all_architectures[] =
{
/* ARM Architectures */
/* We don't specify tuning costs here as it will be figured out
from the core. */
#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA) \
{NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
{ISA isa_nobit}, NULL},
#include "arm-arches.def"
#undef ARM_ARCH
{NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
};
/* Auto-generated CPU, FPU and architecture tables. */
#include "arm-cpu-data.h"
/* The name of the preprocessor macro to define for this architecture. PROFILE
is replaced by the architecture name (eg. 8A) in arm_option_override () and
@ -2327,17 +2302,6 @@ static const struct processors all_architectures[] =
char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
/* Available values for -mfpu=. */
const struct arm_fpu_desc all_fpus[] =
{
#undef ARM_FPU
#define ARM_FPU(NAME, CNAME, ISA) \
{ NAME, {ISA isa_nobit} },
#include "arm-fpus.def"
#undef ARM_FPU
};
/* Supported TLS relocations. */
enum tls_reloc {

98
gcc/config/arm/genopt.sh
View File

@ -1,98 +0,0 @@
#!/bin/sh
# Generate arm-tables.opt from the lists in *.def.
# Copyright (C) 2011-2017 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
cat <<EOF
; -*- buffer-read-only: t -*-
; Generated automatically by genopt.sh from arm-cores.def, arm-arches.def
; and arm-fpus.def.
; Copyright (C) 2011-2017 Free Software Foundation, Inc.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
; for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3. If not see
; <http://www.gnu.org/licenses/>.
Enum
Name(processor_type) Type(enum processor_type)
Known ARM CPUs (for use with the -mcpu= and -mtune= options):
EOF
awk -F'[(, ]+' '/^ARM_CORE/ {
name = $2
enum = $3
gsub("\"", "", name)
print "EnumValue"
print "Enum(processor_type) String(" name ") Value( TARGET_CPU_" enum ")"
print ""
}' $1/arm-cores.def
cat <<EOF
Enum
Name(arm_arch) Type(int)
Known ARM architectures (for use with the -march= option):
EOF
awk -F'[(, ]+' 'BEGIN {
value = 0
}
/^ARM_ARCH/ {
name = $2
gsub("\"", "", name)
print "EnumValue"
print "Enum(arm_arch) String(" name ") Value(" value ")"
print ""
value++
}' $1/arm-arches.def
cat <<EOF
Enum
Name(arm_fpu) Type(enum fpu_type)
Known ARM FPUs (for use with the -mfpu= option):
EOF
awk -F'[(, ]+' '
/^ARM_FPU/ {
name = $2
enum = $3
gsub("\"", "", name)
print "EnumValue"
print "Enum(arm_fpu) String(" name ") Value(TARGET_FPU_" enum ")"
print ""
}
END {
print "EnumValue"
print "Enum(arm_fpu) String(auto) Value(TARGET_FPU_auto)"
}' $1/arm-fpus.def

29
gcc/config/arm/gentune.sh
View File

@ -1,29 +0,0 @@
#!/bin/sh
# Generate arm-tune.md, a file containing the tune attribute from the list of
# CPUs in arm-cores.def
# Copyright (C) 2004-2017 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
echo ";; -*- buffer-read-only: t -*-"
echo ";; Generated automatically by gentune.sh from arm-cores.def"
allcores=`awk -F'[(, ]+' '/^ARM_CORE/ { cores = cores$3"," } END { print cores } ' $1`
echo "(define_attr \"tune\""
echo " \"$allcores\"" | sed -e 's/,"$/"/' | sed -e 's/\([a-z0-9_]\+,[a-z0-9_]\+,[a-z0-9_]\+,\)/\1\n\t/g'
echo " (const (symbol_ref \"((enum attr_tune) arm_tune)\")))"

491
gcc/config/arm/parsecpu.awk Normal file
View File

@ -0,0 +1,491 @@
# Manipulate the CPU, FPU and architecture descriptions for ARM.
# Copyright (C) 2017 Free Software Foundation, Inc.
#
# This file is part of GCC.
#
# GCC is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3, or (at your option)
# any later version.
#
# GCC is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
# Invoke this with '-v cmd=<cmd>"
# where <cmd> is one of:
# data: Print the standard 'C' data tables for the CPUs
# common-data: Print the 'C' data for shared driver/compiler files
# headers: Print the standard 'C' headers for the CPUs
# md: Print the machine description fragment
# opt: Print the option tables fragment
# chkcpu <name>: Checks that <name> is a valid CPU
# chktune <name>: Checks that <name> is a valid CPU
# chkfpu <name>: Checks that <name> is a valid FPU
# chkarch <name>: Checks that <arch> is a valid architecture
function fatal (m) {
print "error ("lineno"): " m > "/dev/stderr"
exit 1
}
function toplevel () {
if (cpu_name != "") fatal("missing \"end cpu\"")
if (arch_name != "") fatal("missing \"end arch\"")
if (fpu_name != "") fatal("missing \"end fpu\"")
}
function boilerplate (style) {
ce = ""
if (style == "C" ) {
cs = "/* "
cc = " "
ce = " */"
} else if (style == "md") {
cc = "; "
cs = cc
} else if (style == "sh") {
cc = "# "
cs = cc
} else fatal("Unknown comment style: "style)
print cs "-*- buffer-read-only: t -*-"
print cc "Generated automatically by parsecpu.awk from arm-cpus.in."
print cc "Do not edit."
print ""
print cc "Copyright (C) 2011-2017 Free Software Foundation, Inc."
print ""
print cc "This file is part of GCC."
print ""
print cc "GCC is free software; you can redistribute it and/or modify"
print cc "it under the terms of the GNU General Public License as"
print cc "published by the Free Software Foundation; either version 3,"
print cc "or (at your option) any later version."
print ""
print cc "GCC is distributed in the hope that it will be useful,"
print cc "but WITHOUT ANY WARRANTY; without even the implied warranty of"
print cc "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the"
print cc "GNU General Public License for more details."
print ""
print cc "You should have received a copy of the GNU General Public"
print cc "License along with GCC; see the file COPYING3. If not see"
print cc "<http://www.gnu.org/licenses/>." ce
print ""
}
function tune_flag_pfx (f) {
return "TF_" f
}
function isa_pfx (f) {
if (f ~ /^(bit|quirk)_.*/) return "isa_" f
return "ISA_" f
}
function gen_headers () {
boilerplate("C")
print "enum processor_type"
print "{"
ncpus = split (cpu_list, cpus)
for (n = 1; n <= ncpus; n++) {
print " TARGET_CPU_"cpu_cnames[cpus[n]]","
}
print " TARGET_CPU_arm_none"
print "};\n"
print "enum fpu_type"
print "{"
nfpus = split (fpu_list, fpus)
for (n = 1; n <= nfpus; n++) {
print " TARGET_FPU_"fpu_cnames[fpus[n]]","
}
print " TARGET_FPU_auto"
print "};"
}
function gen_data () {
boilerplate("C")
print "static const struct processors all_cores[] ="
print "{"
ncpus = split (cpu_list, cpus)
for (n = 1; n <= ncpus; n++) {
print " {"
print " \"" cpus[n] "\", TARGET_CPU_" cpu_cnames[cpus[n]] ","
if (cpus[n] in cpu_tune_flags) {
print " (" cpu_tune_flags[cpus[n]] "),"
} else print " 0,"
if (! (cpu_arch[cpus[n]] in arch_isa)) {
fatal("unknown arch " cpu_arch[cpus[n]] " for cpu " cpus[n])
}
print " \"" arch_base[cpu_arch[cpus[n]]] "\", BASE_ARCH_" \
arch_base[cpu_arch[cpus[n]]] ","
print " {"
print " " arch_isa[cpu_arch[cpus[n]]] ","
if (cpus[n] in cpu_fpu) print " " fpu_isa[cpu_fpu[cpus[n]]] ","
if (cpus[n] in cpu_isa) print " " cpu_isa[cpus[n]] ","
print " isa_nobit"
print " },"
print " &arm_" cpu_cost[cpus[n]] "_tune"
print " },"
}
print " {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \
" {isa_nobit}, NULL}"
print "};\n"
print "static const struct processors all_architectures[] ="
print "{"
narchs = split (arch_list, archs)
for (n = 1; n <= narchs; n++) {
print " {"
if (! (arch_tune_for[archs[n]] in cpu_cnames)) {
fatal("unknown \"tune for\" target " arch_tune_for[archs[n]] \
"for architecture " archs[n])
}
print " \"" archs[n] \
"\", TARGET_CPU_" cpu_cnames[arch_tune_for[archs[n]]] ","
if (archs[n] in arch_tune_flags) {
print " (" arch_tune_flags[archs[n]] "),"
} else print " 0,"
print " \"" arch_base[archs[n]] "\", BASE_ARCH_" \
arch_base[archs[n]] ","
print " {"
print " " arch_isa[archs[n]] ","
print " isa_nobit"
print " },"
print " NULL"
print " },"
}
print " {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0," \
" {isa_nobit}, NULL}"
print "};\n"
print "const struct arm_fpu_desc all_fpus[] ="
print "{"
nfpus = split (fpu_list, fpus)
for (n = 1; n <= nfpus; n++) {
print " {"
print " \"" fpus[n] "\","
print " {"
print " " fpu_isa[fpus[n]] ","
print " isa_nobit"
print " }"
print " },"
}
print "};"
}
function gen_comm_data () {
boilerplate("C")
print "static const struct arm_arch_core_flag arm_arch_core_flags[] ="
print "{"
ncpus = split (cpu_list, cpus)
for (n = 1; n <= ncpus; n++) {
print " {"
print " \"" cpus[n] "\","
if (! (cpu_arch[cpus[n]] in arch_isa)) {
fatal("unknown arch " cpu_arch[cpus[n]] " for cpu " cpus[n])
}
print " {"
print " " arch_isa[cpu_arch[cpus[n]]] ","
if (cpus[n] in cpu_fpu) print " " fpu_isa[cpu_fpu[cpus[n]]] ","
if (cpus[n] in cpu_isa) print " " cpu_isa[cpus[n]] ","
print " isa_nobit"
print " },"
print " },"
}
narchs = split (arch_list, archs)
for (n = 1; n <= narchs; n++) {
print " {"
print " \"" archs[n] "\","
print " {"
print " " arch_isa[archs[n]] ","
print " isa_nobit"
print " },"
print " },"
}
print "};\n"
}
function gen_md () {
boilerplate("md")
z = ORS
ORS = ""
print "(define_attr \"tune\"\n\t\""
ncpus = split (cpu_list, cpus)
for (n = 1; n < ncpus; n++) {
if ((n % 3) != 0) {
ORS = ","
} else ORS = ",\n\t"
print cpu_cnames[cpus[n]]
}
ORS = z
print cpu_cnames[cpus[ncpus]]"\""
print "\t(const (symbol_ref \"((enum attr_tune) arm_tune)\")))"
}
function gen_opt () {
boilerplate("md")
print "Enum"
print "Name(processor_type) Type(enum processor_type)"
print "Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n"
ncpus = split (cpu_list, cpus)
for (n = 1; n <= ncpus; n++) {
print "EnumValue"
print "Enum(processor_type) String(" cpus[n] \
") Value( TARGET_CPU_"cpu_cnames[cpus[n]]")"
print ""
}
print "Enum"
print "Name(arm_arch) Type(int)"
print "Known ARM architectures (for use with the -march= option):\n"
narchs = split (arch_list, archs)
for (n = 1; n <= narchs; n++) {
print "EnumValue"
print "Enum(arm_arch) String(" archs[n] \
") Value("n - 1")"
print ""
}
print "Enum"
print "Name(arm_fpu) Type(enum fpu_type)"
print "Known ARM FPUs (for use with the -mfpu= option):\n"
nfpus = split (fpu_list, fpus)
for (n = 1; n <= nfpus; n++) {
print "EnumValue"
print "Enum(arm_fpu) String(" fpus[n] \
") Value(TARGET_FPU_"fpu_cnames[fpus[n]]")"
print ""
}
print "EnumValue"
print "Enum(arm_fpu) String(auto) Value(TARGET_FPU_auto)"
}
function check_cpu (name) {
if (name in cpu_cnames) {
print cpu_cnames[name]
} else print "error"
}
function check_fpu (name) {
if (name in fpu_cnames) {
print fpu_cnames[name]
} else print "error"
}
function check_arch (name) {
if (name in arch_isa) {
print name
} else print "error"
}
BEGIN {
cpu_name = ""
arch_name = ""
fpu_name = ""
lineno = 0
if (cmd == "") fatal("Usage parsecpu.awk -v cmd=<xyz>")
}
// {
lineno++
parse_ok = 0
}
/^#/ {
parse_ok = 1
}
/^begin fpu / {
toplevel()
fpu_name = $3
parse_ok = 1
}
/^end fpu / {
if (fpu_name != $3) fatal("mimatched end fpu")
if (! (fpu_name in fpu_isa)) {
fatal("fpu definition \"" fpu_name "\" lacks an \"isa\" statement")
}
fpu_cnames[fpu_name] = fpu_name
gsub(/[-+.]/, "_", fpu_cnames[fpu_name])
fpu_list = fpu_list " " fpu_name
fpu_name = ""
parse_ok = 1
}
/^begin arch / {
toplevel()
arch_name = $3
parse_ok = 1
}
/^[ ]*base / {
if (arch_name == "") fatal("\"base\" statement outside of arch block")
arch_base[arch_name] = $2
parse_ok = 1
}
/^end arch / {
if (arch_name != $3) fatal("mimatched end arch")
if (! arch_name in arch_tune_for) {
fatal("arch definition lacks a \"tune for\" statement")
}
if (! arch_name in arch_isa) {
fatal("arch definition lacks an \"isa\" statement")
}
arch_list = arch_list " " arch_name
arch_name = ""
parse_ok = 1
}
/^begin cpu / {
toplevel()
cpu_name = $3
parse_ok = 1
}
/^[ ]*cname / {
if (cpu_name == "") fatal("\"cname\" outside of cpu block")
cpu_cnames[cpu_name] = $2
parse_ok = 1
}
/^[ ]*tune for / {
if (cpu_name != "") {
cpu_tune_for[cpu_name] = $3
} else if (arch_name != "") {
arch_tune_for[arch_name] = $3
} else fatal("\"tune for\" outside of cpu or arch block")
parse_ok = 1
}
/^[ ]*tune flags / {
flags=""
flag_count = NF
for (n = 3; n <= flag_count; n++) {
if (n == 3) {
flags = tune_flag_pfx($n)
} else flags = flags " | " tune_flag_pfx($n)
}
if (cpu_name != "") {
cpu_tune_flags[cpu_name] = flags
} else if (arch_name != "") {
arch_tune_flags[arch_name] = flags
} else fatal("\"tune flags\" outside of cpu or arch block")
parse_ok = 1
}
/^[ ]*architecture / {
if (cpu_name == "") fatal("\"architecture\" outside of cpu block")
cpu_arch[cpu_name] = $2
parse_ok = 1
}
/^[ ]*fpu / {
if (cpu_name == "") fatal("\"fpu\" outside of cpu block")
cpu_fpu[cpu_name] = $2
parse_ok = 1
}
/^[ ]*isa / {
flags=""
flag_count = NF
for (n = 2; n <= flag_count; n++) {
if (n == 2) {
flags = isa_pfx($n)
} else flags = flags "," isa_pfx($n)
}
if (cpu_name != "") {
cpu_isa[cpu_name] = flags
} else if (arch_name != "") {
arch_isa[arch_name] = flags
} else if (fpu_name != "") {
fpu_isa[fpu_name] = flags
} else fatal("\"isa\" outside of cpu, fpu or arch block")
parse_ok = 1
}
/^[ ]*costs / {
if (cpu_name == "") fatal("\"costs\" outside of cpu block")
cpu_cost[cpu_name] = $2
parse_ok = 1
}
/^end cpu / {
if (cpu_name != $3) fatal("mimatched end cpu")
if (! (cpu_name in cpu_cnames)) {
cpu_cnames[cpu_name] = cpu_name
gsub(/[-+.]/, "_", cpu_cnames[cpu_name])
}
if (! cpu_name in cpu_arch) fatal("cpu definition lacks an architecture")
cpu_list = cpu_list " " cpu_name
cpu_name = ""
parse_ok = 1
}
/[^\s]/ {
if (! parse_ok) fatal("Unrecognized statement: " $0)
}
END {
toplevel()
if (cmd == "data") {
gen_data()
} else if (cmd == "common-data") {
gen_comm_data()
} else if (cmd == "headers") {
gen_headers()
} else if (cmd == "md") {
gen_md()
} else if (cmd == "opt") {
gen_opt()
} else if (cmd ~ /^chk(cpu|tune) /) {
split (cmd, target)
check_cpu(target[2])
} else if (cmd ~ /^chkarch /) {
split (cmd, target)
check_arch(target[2])
} else if (cmd ~ /^chkfpu /) {
split (cmd, target)
check_fpu(target[2])
} else fatal("unrecognized command: "cmd)
}

44
gcc/config/arm/t-arm
View File

@ -18,8 +18,7 @@
# along with GCC; see the file COPYING3. If not see
# <http://www.gnu.org/licenses/>.
TM_H += $(srcdir)/config/arm/arm-cores.def
OPTIONS_H_EXTRA += $(srcdir)/config/arm/arm-cores.def
TM_H += $(srcdir)/config/arm/arm-cpu.h
# All md files - except for arm.md.
# This list should be kept in alphabetical order and updated whenever an md
@ -67,18 +66,36 @@ MD_INCLUDES= $(srcdir)/config/arm/arm1020e.md \
s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
$(srcdir)/config/arm/arm-tune.md: $(srcdir)/config/arm/gentune.sh \
$(srcdir)/config/arm/arm-cores.def
$(SHELL) $(srcdir)/config/arm/gentune.sh \
$(srcdir)/config/arm/arm-cores.def > \
$(srcdir)/config/arm/arm-tune.md
$(srcdir)/config/arm/arm-tune.md: $(srcdir)/config/arm/parsecpu.awk \
$(srcdir)/config/arm/arm-cpus.in
$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=md \
$(srcdir)/config/arm/arm-cpus.in > arm-tune.new
mv arm-tune.new $(srcdir)/config/arm/arm-tune.md
$(srcdir)/config/arm/arm-tables.opt: $(srcdir)/config/arm/genopt.sh \
$(srcdir)/config/arm/arm-cores.def $(srcdir)/config/arm/arm-arches.def \
$(srcdir)/config/arm/arm-fpus.def
$(SHELL) $(srcdir)/config/arm/genopt.sh $(srcdir)/config/arm > \
$(srcdir)/config/arm/arm-tables.opt: $(srcdir)/config/arm/parsecpu.awk \
$(srcdir)/config/arm/arm-cpus.in
$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=opt \
$(srcdir)/config/arm/arm-cpus.in > \
$(srcdir)/config/arm/arm-tables.opt
$(srcdir)/config/arm/arm-cpu.h: $(srcdir)/config/arm/parsecpu.awk \
$(srcdir)/config/arm/arm-cpus.in
$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=headers \
$(srcdir)/config/arm/arm-cpus.in > arm-cpu.new
mv arm-cpu.new $(srcdir)/config/arm/arm-cpu.h
$(srcdir)/config/arm/arm-cpu-data.h: $(srcdir)/config/arm/parsecpu.awk \
$(srcdir)/config/arm/arm-cpus.in
$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=data \
$(srcdir)/config/arm/arm-cpus.in > arm-cpu-data.new
mv arm-cpu-data.new $(srcdir)/config/arm/arm-cpu-data.h
$(srcdir)/config/arm/arm-cpu-cdata.h: $(srcdir)/config/arm/parsecpu.awk \
$(srcdir)/config/arm/arm-cpus.in
$(AWK) -f $(srcdir)/config/arm/parsecpu.awk -v cmd=common-data \
$(srcdir)/config/arm/arm-cpus.in > arm-cpu-cdata.new
mv arm-cpu-cdata.new $(srcdir)/config/arm/arm-cpu-cdata.h
aarch-common.o: $(srcdir)/config/arm/aarch-common.c $(CONFIG_H) $(SYSTEM_H) \
coretypes.h $(TM_H) $(TM_P_H) $(RTL_H) $(TREE_H) output.h $(C_COMMON_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
@ -92,8 +109,7 @@ arm.o: $(srcdir)/config/arm/arm.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \
$(GGC_H) except.h $(C_PRAGMA_H) $(TM_P_H) \
$(TARGET_H) $(TARGET_DEF_H) debug.h langhooks.h $(DF_H) \
intl.h libfuncs.h $(PARAMS_H) $(OPTS_H) sched-int.h \
$(srcdir)/config/arm/arm-cores.def \
$(srcdir)/config/arm/arm-arches.def $(srcdir)/config/arm/arm-fpus.def \
$(srcdir)/config/arm/arm-cpu-data.h \
$(srcdir)/config/arm/arm-protos.h \
$(srcdir)/config/arm/arm_neon_builtins.def \
$(srcdir)/config/arm/arm_vfp_builtins.def
@ -113,3 +129,5 @@ arm-c.o: $(srcdir)/config/arm/arm-c.c $(CONFIG_H) $(SYSTEM_H) \
coretypes.h $(TM_H) $(TREE_H) output.h $(C_COMMON_H)
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/arm/arm-c.c
arm-common.o: $(srcdir)/config/arm/arm-cpu-cdata.h