mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-04-04 04:40:27 +08:00
Code Issues Packages Projects Releases Wiki Activity

pa.c (output_move_double): Handle loading a general register from a scaled indexed memory address.

Browse Source 
* pa.c (output_move_double): Handle loading a general register
        from a scaled indexed memory address.
        * pa.md (movdf, movdi): Allow scaled loads into general registers.

From-SVN: r14073
This commit is contained in:
Jeff Law 1997-05-16 14:58:24 -06:00
parent 30ccf55d85
commit a89974a23e
2 changed files with 31 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
gcc/config/pa/pa.c
View File

@ -1662,6 +1662,35 @@ output_move_double (operands)
return "ldw -4(0,%1),%R0\n\tldws,mb -8(0,%1),%0";
}
}
else if (GET_CODE (addr) == PLUS
&& GET_CODE (XEXP (addr, 0)) == MULT)
{
rtx high_reg = gen_rtx (SUBREG, SImode, operands[0], 0);
if (!reg_overlap_mentioned_p (high_reg, addr))
{
rtx xoperands[3];
xoperands[0] = high_reg;
xoperands[1] = XEXP (addr, 1);
xoperands[2] = XEXP (XEXP (addr, 0), 0);
xoperands[3] = XEXP (XEXP (addr, 0), 1);
output_asm_insn ("sh%O3addl %2,%1,%0", xoperands);
return "ldw 4(0,%0),%R0\n\tldw 0(0,%0),%0";
}
else
{
rtx xoperands[3];
xoperands[0] = high_reg;
xoperands[1] = XEXP (addr, 1);
xoperands[2] = XEXP (XEXP (addr, 0), 0);
xoperands[3] = XEXP (XEXP (addr, 0), 1);
output_asm_insn ("sh%O3addl %2,%1,%R0", xoperands);
return "ldw 0(0,%R0),%0\n\tldw 4(0,%R0),%R0";
}
}
}
/* If an operand is an unoffsettable memory ref, find a register

4
gcc/config/pa/pa.md
View File

@ -2234,7 +2234,7 @@
[(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
"=f,*r,RQ,?o,?Q,f,*r,*r")
(match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
"fG,*rG,f,*r,*r,RQ,o,Q"))]
"fG,*rG,f,*r,*r,RQ,o,RQ"))]
"(register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))
&& ! (GET_CODE (operands[1]) == CONST_DOUBLE
@ -2425,7 +2425,7 @@
[(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
"=r,o,Q,r,r,r,f,f,*TR")
(match_operand:DI 1 "general_operand"
"rM,r,r,o,Q,i,fM,*TR,f"))]
"rM,r,r,o*R,Q,i,fM,*TR,f"))]
"(register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))
&& ! TARGET_SOFT_FLOAT"