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[arm] Add initial support for Arm Cortex-M55
This patch adds initial -mcpu support for the Arm Cortex-M55 CPU. This CPU is an Armv8.1-M Mainline CPU supporting MVE. An option to disable floating-point (and MVE) is provided with the +nofp. For GCC 11 I'd like to add further fine-grained options to enable integer-only MVE but that needs a bit more elaborate surgery in arm-cpus.in that I don't want to do in GCC 10 at this stage. As this CPU is not supported in gas and I don't want to couple GCC 10 to the very latest binutils anyway, this CPU emits the cpu string in the assembly file as a build attribute rather than a .cpu directive, thus sparing us the need to support .cpu cortex-m55 in gas. The .cpu directive in gas isn't used for anything besides setting the Tag_CPU_name build attribute anyway (which itself is not used by any tools I'm aware of). All the architecture information used for target detection is already emitted using .arch_extension directives and similar. Bootstrapped and tested on arm-none-linux-gnueabihf. Also tested on arm-none-eabi. 2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Andre Vieira <andre.simoesdiasvieira@arm.com> Mihail Ionescu <mihail.ionescu@arm.com> * config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu. * config/arm/arm-cpus.in (quirk_no_asmcpu): Define. (ALL_QUIRKS): Add quirk_no_asmcpu. (cortex-m55): Define new cpu. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
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@ -1,3 +1,15 @@
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2020-04-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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Andre Vieira <andre.simoesdiasvieira@arm.com>
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Mihail Ionescu <mihail.ionescu@arm.com>
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* config/arm/arm.c (arm_file_start): Handle isa_bit_quirk_no_asmcpu.
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* config/arm/arm-cpus.in (quirk_no_asmcpu): Define.
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(ALL_QUIRKS): Add quirk_no_asmcpu.
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(cortex-m55): Define new cpu.
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* config/arm/arm-tables.opt: Regenerate.
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* config/arm/arm-tune.md: Likewise.
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* doc/invoke.texi (Arm Options): Document -mcpu=cortex-m55.
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2020-04-22 Richard Sandiford <richard.sandiford@arm.com>
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PR tree-optimization/94700
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@ -190,6 +190,9 @@ define feature quirk_armv6kz
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# Cortex-M3 LDRD quirk.
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define feature quirk_cm3_ldrd
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# Don't use .cpu assembly directive
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define feature quirk_no_asmcpu
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# (Very) slow multiply operations. Should probably be a tuning bit.
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define feature smallmul
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@ -311,7 +314,7 @@ define fgroup DOTPROD NEON dotprod
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# architectures.
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# xscale isn't really a 'quirk', but it isn't an architecture either and we
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# need to ignore it for matching purposes.
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define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd xscale
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define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd xscale quirk_no_asmcpu
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# Architecture entries
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# format:
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@ -1501,6 +1504,16 @@ begin cpu cortex-m35p
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costs v7m
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end cpu cortex-m35p
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begin cpu cortex-m55
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cname cortexm55
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tune flags LDSCHED
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architecture armv8.1-m.main+mve.fp+fp.dp
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isa quirk_no_asmcpu
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option nofp remove ALL_FP MVE_FP
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costs v7m
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vendor 41
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end cpu cortex-m55
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# V8 R-profile implementations.
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begin cpu cortex-r52
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cname cortexr52
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@ -258,6 +258,9 @@ Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
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EnumValue
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Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p)
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EnumValue
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Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55)
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EnumValue
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Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
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@ -47,5 +47,5 @@
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cortexa76,cortexa76ae,cortexa77,
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neoversen1,cortexa75cortexa55,cortexa76cortexa55,
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cortexm23,cortexm33,cortexm35p,
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cortexr52"
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cortexm55,cortexr52"
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(const (symbol_ref "((enum attr_tune) arm_tune)")))
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@ -27889,7 +27889,11 @@ arm_file_start (void)
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{
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const char* truncated_name
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= arm_rewrite_selected_cpu (arm_active_target.core_name);
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asm_fprintf (asm_out_file, "\t.cpu %s\n", truncated_name);
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if (bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_no_asmcpu))
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asm_fprintf (asm_out_file, "\t.eabi_attribute 5, \"%s\"\n",
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truncated_name);
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else
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asm_fprintf (asm_out_file, "\t.cpu %s\n", truncated_name);
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}
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if (print_tune_info)
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@ -18773,7 +18773,7 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
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@samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
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@samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
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@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
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@samp{cortex-m35p},
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@samp{cortex-m35p}, @samp{cortex-m55},
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@samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
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@samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
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@samp{neoverse-n1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2},
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@ -18850,7 +18850,7 @@ Disables the floating-point and SIMD instructions on
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@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
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@samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a15.cortex-a7},
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@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35},
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@samp{cortex-a53} and @samp{cortex-a55}.
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@samp{cortex-a53},@samp{cortex-a55} and @samp{cortex-m55}.
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@item +nofp.dp
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Disables the double-precision component of the floating-point instructions
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