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[AArch64] Add support for SVE HF vconds
We were missing vcond patterns that had HF comparisons and HI or HF data. 2019-08-14 Richard Sandiford <richard.sandiford@arm.com> gcc/ * config/aarch64/iterators.md (SVE_HSD): New mode iterator. (V_FP_EQUIV, v_fp_equiv): Handle VNx8HI and VNx8HF. * config/aarch64/aarch64-sve.md (vcond<mode><v_fp_equiv>): Use SVE_HSD instead of SVE_SD. gcc/testsuite/ * gcc.target/aarch64/sve/vcond_17.c: New test. * gcc.target/aarch64/sve/vcond_17_run.c: Likewise. From-SVN: r274420
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Richard Sandiford
Richard Sandiford
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commit
a70965b114
@ -1,3 +1,10 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* config/aarch64/iterators.md (SVE_HSD): New mode iterator.
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(V_FP_EQUIV, v_fp_equiv): Handle VNx8HI and VNx8HF.
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* config/aarch64/aarch64-sve.md (vcond<mode><v_fp_equiv>): Use
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SVE_HSD instead of SVE_SD.
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
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@ -2884,13 +2884,13 @@
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;; Floating-point vcond. All comparisons except FCMUO allow a zero operand;
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;; aarch64_expand_sve_vcond handles the case of an FCMUO with zero.
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(define_expand "vcond<mode><v_fp_equiv>"
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[(set (match_operand:SVE_SD 0 "register_operand")
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(if_then_else:SVE_SD
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[(set (match_operand:SVE_HSD 0 "register_operand")
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(if_then_else:SVE_HSD
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(match_operator 3 "comparison_operator"
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[(match_operand:<V_FP_EQUIV> 4 "register_operand")
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(match_operand:<V_FP_EQUIV> 5 "aarch64_simd_reg_or_zero")])
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(match_operand:SVE_SD 1 "register_operand")
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(match_operand:SVE_SD 2 "register_operand")))]
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(match_operand:SVE_HSD 1 "register_operand")
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(match_operand:SVE_HSD 2 "register_operand")))]
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"TARGET_SVE"
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{
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aarch64_expand_sve_vcond (<MODE>mode, <V_FP_EQUIV>mode, operands);
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@ -301,6 +301,9 @@
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;; All SVE floating-point vector modes that have 16-bit or 32-bit elements.
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(define_mode_iterator SVE_HSF [VNx8HF VNx4SF])
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;; All SVE vector modes that have 16-bit, 32-bit or 64-bit elements.
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(define_mode_iterator SVE_HSD [VNx8HI VNx4SI VNx2DI VNx8HF VNx4SF VNx2DF])
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;; All SVE vector modes that have 32-bit or 64-bit elements.
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(define_mode_iterator SVE_SD [VNx4SI VNx2DI VNx4SF VNx2DF])
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@ -928,9 +931,11 @@
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])
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;; Floating-point equivalent of selected modes.
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(define_mode_attr V_FP_EQUIV [(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
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(define_mode_attr V_FP_EQUIV [(VNx8HI "VNx8HF") (VNx8HF "VNx8HF")
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(VNx4SI "VNx4SF") (VNx4SF "VNx4SF")
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(VNx2DI "VNx2DF") (VNx2DF "VNx2DF")])
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(define_mode_attr v_fp_equiv [(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
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(define_mode_attr v_fp_equiv [(VNx8HI "vnx8hf") (VNx8HF "vnx8hf")
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(VNx4SI "vnx4sf") (VNx4SF "vnx4sf")
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(VNx2DI "vnx2df") (VNx2DF "vnx2df")])
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;; Mode for vector conditional operations where the comparison has
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@ -1,3 +1,8 @@
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/vcond_17.c: New test.
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* gcc.target/aarch64/sve/vcond_17_run.c: Likewise.
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2019-08-14 Richard Sandiford <richard.sandiford@arm.com>
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* gcc.target/aarch64/sve/spill_4.c: Expect all ptrues to be .Bs.
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94
gcc/testsuite/gcc.target/aarch64/sve/vcond_17.c
Normal file
94
gcc/testsuite/gcc.target/aarch64/sve/vcond_17.c
Normal file
@ -0,0 +1,94 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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#include <stdint.h>
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#define eq(A, B) ((A) == (B))
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#define ne(A, B) ((A) != (B))
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#define olt(A, B) ((A) < (B))
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#define ole(A, B) ((A) <= (B))
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#define oge(A, B) ((A) >= (B))
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#define ogt(A, B) ((A) > (B))
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#define ordered(A, B) (!__builtin_isunordered (A, B))
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#define unordered(A, B) (__builtin_isunordered (A, B))
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#define ueq(A, B) (!__builtin_islessgreater (A, B))
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#define ult(A, B) (__builtin_isless (A, B))
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#define ule(A, B) (__builtin_islessequal (A, B))
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#define uge(A, B) (__builtin_isgreaterequal (A, B))
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#define ugt(A, B) (__builtin_isgreater (A, B))
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#define nueq(A, B) (__builtin_islessgreater (A, B))
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#define nult(A, B) (!__builtin_isless (A, B))
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#define nule(A, B) (!__builtin_islessequal (A, B))
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#define nuge(A, B) (!__builtin_isgreaterequal (A, B))
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#define nugt(A, B) (!__builtin_isgreater (A, B))
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#define DEF_LOOP(CMP, EXPECT_INVALID) \
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void __attribute__ ((noinline, noclone)) \
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test_##CMP##_var (__fp16 *restrict dest, __fp16 *restrict src, \
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__fp16 fallback, __fp16 *restrict a, \
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__fp16 *restrict b, int count) \
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{ \
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for (int i = 0; i < count; ++i) \
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dest[i] = CMP (a[i], b[i]) ? src[i] : fallback; \
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} \
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\
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void __attribute__ ((noinline, noclone)) \
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test_##CMP##_zero (__fp16 *restrict dest, __fp16 *restrict src, \
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__fp16 fallback, __fp16 *restrict a, \
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int count) \
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{ \
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for (int i = 0; i < count; ++i) \
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dest[i] = CMP (a[i], (__fp16) 0) ? src[i] : fallback; \
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} \
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\
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void __attribute__ ((noinline, noclone)) \
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test_##CMP##_sel (__fp16 *restrict dest, __fp16 if_true, \
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__fp16 if_false, __fp16 *restrict a, \
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__fp16 b, int count) \
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{ \
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for (int i = 0; i < count; ++i) \
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dest[i] = CMP (a[i], b) ? if_true : if_false; \
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}
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#define TEST_ALL(T) \
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T (eq, 0) \
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T (ne, 0) \
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T (olt, 1) \
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T (ole, 1) \
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T (oge, 1) \
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T (ogt, 1) \
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T (ordered, 0) \
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T (unordered, 0) \
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T (ueq, 0) \
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T (ult, 0) \
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T (ule, 0) \
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T (uge, 0) \
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T (ugt, 0) \
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T (nueq, 0) \
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T (nult, 0) \
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T (nule, 0) \
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T (nuge, 0) \
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T (nugt, 0)
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TEST_ALL (DEF_LOOP)
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/* { dg-final { scan-assembler {\tfcmeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\.0\n} { xfail *-*-* } } } */
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/* { dg-final { scan-assembler {\tfcmeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tfcmne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\.0\n} } } */
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/* { dg-final { scan-assembler {\tfcmne\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tfcmlt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\.0\n} } } */
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/* { dg-final { scan-assembler {\tfcmlt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tfcmle\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\.0\n} } } */
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/* { dg-final { scan-assembler {\tfcmle\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tfcmgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\.0\n} } } */
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/* { dg-final { scan-assembler {\tfcmgt\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler {\tfcmge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\.0\n} } } */
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/* { dg-final { scan-assembler {\tfcmge\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
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/* { dg-final { scan-assembler-not {\tfcmuo\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, #0\.0\n} } } */
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/* { dg-final { scan-assembler {\tfcmuo\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} } } */
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54
gcc/testsuite/gcc.target/aarch64/sve/vcond_17_run.c
Normal file
54
gcc/testsuite/gcc.target/aarch64/sve/vcond_17_run.c
Normal file
@ -0,0 +1,54 @@
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/* { dg-do run { target aarch64_sve_hw } } */
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/* { dg-options "-O2 -ftree-vectorize" } */
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/* { dg-require-effective-target fenv_exceptions } */
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#include <fenv.h>
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#include "vcond_17.c"
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#define N 401
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#define TEST_LOOP(CMP, EXPECT_INVALID) \
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{ \
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__fp16 dest1[N], dest2[N], dest3[N], src[N]; \
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__fp16 a[N], b[N]; \
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for (int i = 0; i < N; ++i) \
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{ \
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src[i] = i * i; \
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if (i % 5 == 0) \
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a[i] = 0; \
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else if (i % 3) \
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a[i] = i * 0.1; \
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else \
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a[i] = i; \
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if (i % 7 == 0) \
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b[i] = __builtin_nan (""); \
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else if (i % 6) \
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b[i] = i * 0.1; \
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else \
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b[i] = i; \
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asm volatile ("" ::: "memory"); \
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} \
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feclearexcept (FE_ALL_EXCEPT); \
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test_##CMP##_var (dest1, src, 11, a, b, N); \
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test_##CMP##_zero (dest2, src, 22, a, N); \
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test_##CMP##_sel (dest3, 33, 44, a, 9, N); \
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if (!fetestexcept (FE_INVALID) != !(EXPECT_INVALID)) \
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__builtin_abort (); \
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for (int i = 0; i < N; ++i) \
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{ \
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if (dest1[i] != (CMP (a[i], b[i]) ? src[i] : 11)) \
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__builtin_abort (); \
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if (dest2[i] != (CMP (a[i], 0) ? src[i] : 22)) \
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__builtin_abort (); \
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if (dest3[i] != (CMP (a[i], 9) ? 33 : 44)) \
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__builtin_abort (); \
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} \
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}
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int __attribute__ ((optimize (1)))
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main (void)
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{
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TEST_ALL (TEST_LOOP)
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return 0;
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}
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