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Fix twolf ICE for ARM

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2009-08-19  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
            Richard Earnshaw  <richard.earnshaw@arm.com>

        * config/arm/arm.c (arm_emit_movpair): Handle CONST_INT.
        * config/arm/arm.md (*arm_movtas_ze): New pattern for
        movt.

2009-08-19  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
            Richard Earnshaw  <richard.earnshaw@arm.com>

        * testsuite/gcc.target/arm/20090811-1.c: New test.

Co-Authored-By: Richard Earnshaw <rearnsha@arm.com>

From-SVN: r150953
This commit is contained in:
Ramana Radhakrishnan 2009-08-20 08:09:29 +00:00 committed by Ramana Radhakrishnan
parent 2fd74bffec
commit a552b644fb
5 changed files with 73 additions and 8 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2009-08-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <richard.earnshaw@arm.com>
* config/arm/arm.c (arm_emit_movpair): Handle CONST_INT.
* config/arm/arm.md (*arm_movtas_ze): New pattern for
movt.
2009-08-19 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* pa.md (reload_inhi, reload_outhi, reload_inqi, reload_outqi): New

25
gcc/config/arm/arm.c
View File

@ -11558,14 +11558,23 @@ output_mov_long_double_arm_from_arm (rtx *operands)
return "";
}
/* Emit a MOVW/MOVT pair. */
void arm_emit_movpair (rtx dest, rtx src)
{
emit_set_insn (dest, gen_rtx_HIGH (SImode, src));
emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src));
}
void
arm_emit_movpair (rtx dest, rtx src)
{
/* If the src is an immediate, simplify it. */
if (CONST_INT_P (src))
{
HOST_WIDE_INT val = INTVAL (src);
emit_set_insn (dest, GEN_INT (val & 0x0000ffff));
if ((val >> 16) & 0x0000ffff)
emit_set_insn (gen_rtx_ZERO_EXTRACT (SImode, dest, GEN_INT (16),
GEN_INT (16)),
GEN_INT ((val >> 16) & 0x0000ffff));
return;
}
emit_set_insn (dest, gen_rtx_HIGH (SImode, src));
emit_set_insn (dest, gen_rtx_LO_SUM (SImode, dest, src));
}
/* Output a move from arm registers to an fpa registers.
OPERANDS[0] is an fpa register.

11
gcc/config/arm/arm.md
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@ -11050,6 +11050,17 @@
[(set_attr "conds" "clob")]
)
(define_insn "*arm_movtas_ze"
[(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
(const_int 16)
(const_int 16))
(match_operand:SI 1 "const_int_operand" ""))]
"TARGET_32BIT"
"movt%?\t%0, %c1"
[(set_attr "predicable" "yes")
(set_attr "length" "4")]
)
;; Load the FPA co-processor patterns
(include "fpa.md")
;; Load the Maverick co-processor patterns

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2009-08-19 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Richard Earnshaw <richard.earnshaw@arm.com>
* testsuite/gcc.target/arm/20090811-1.c: New test.
2009-08-19 Jakub Jelinek <jakub@redhat.com>
PR middle-end/41123

33
gcc/testsuite/gcc.target/arm/20090811-1.c Normal file
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@ -0,0 +1,33 @@
/* { dg-do compile } */
/* { dg-options "-O3 -mcpu=cortex-a8 -mfpu=vfp3 -mfloat-abi=softfp" } */
typedef struct cb
{
int cxc;
short int pside;
} *CBPTR;
typedef struct rwb
{
int stx;
} RWB;
extern CBPTR *car;
extern RWB *rwAr;
extern int nts;
extern int nRws;
void f()
{
CBPTR pptr ;
int k_lt, k_rt, k_span, rw, p, rt;
int sa ;
k_rt = 0;
k_lt = 10000000;
for (rw = 1; rw <= nRws; rw++)
k_lt = rwAr[rw].stx;
k_span = k_rt - k_lt;
for (; p <= nts; p++)
{
pptr = car[p];
if (pptr->pside == 3)
pptr->cxc += (int)(((double)rt / (double) k_span) *((double) sa));
}
}