diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 455b025521f2..6359c40bdecd 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -2925,14 +2925,17 @@ ;; Integer unary arithmetic predicated with a PTRUE. (define_insn "@aarch64_pred_" - [(set (match_operand:SVE_I 0 "register_operand" "=w") + [(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w") (unspec:SVE_I - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (SVE_INT_UNARY:SVE_I - (match_operand:SVE_I 2 "register_operand" "w"))] + (match_operand:SVE_I 2 "register_operand" "0, w"))] UNSPEC_PRED_X))] "TARGET_SVE" - "\t%0., %1/m, %2." + "@ + \t%0., %1/m, %2. + movprfx\t%0, %2\;\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated integer unary arithmetic with merging. @@ -2998,15 +3001,18 @@ ;; Predicated integer unary operations. (define_insn "@aarch64_pred_" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w") + [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") (unspec:SVE_FULL_I - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (unspec:SVE_FULL_I - [(match_operand:SVE_FULL_I 2 "register_operand" "w")] + [(match_operand:SVE_FULL_I 2 "register_operand" "0, w")] SVE_INT_UNARY)] UNSPEC_PRED_X))] "TARGET_SVE && >= " - "\t%0., %1/m, %2." + "@ + \t%0., %1/m, %2. + movprfx\t%0, %2\;\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Another way of expressing the REVB, REVH and REVW patterns, with this @@ -3014,15 +3020,18 @@ ;; of lanes and the data mode decides the granularity of the reversal within ;; each lane. (define_insn "@aarch64_sve_revbhw_" - [(set (match_operand:SVE_ALL 0 "register_operand" "=w") + [(set (match_operand:SVE_ALL 0 "register_operand" "=w, ?&w") (unspec:SVE_ALL - [(match_operand:PRED_HSD 1 "register_operand" "Upl") + [(match_operand:PRED_HSD 1 "register_operand" "Upl, Upl") (unspec:SVE_ALL - [(match_operand:SVE_ALL 2 "register_operand" "w")] + [(match_operand:SVE_ALL 2 "register_operand" "0, w")] UNSPEC_REVBHW)] UNSPEC_PRED_X))] "TARGET_SVE && > " - "rev\t%0., %1/m, %2." + "@ + rev\t%0., %1/m, %2. + movprfx\t%0, %2\;rev\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated integer unary operations with merging. @@ -3071,28 +3080,34 @@ ;; Predicated sign and zero extension from a narrower mode. (define_insn "*2" - [(set (match_operand:SVE_HSDI 0 "register_operand" "=w") + [(set (match_operand:SVE_HSDI 0 "register_operand" "=w, ?&w") (unspec:SVE_HSDI - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (ANY_EXTEND:SVE_HSDI - (match_operand:SVE_PARTIAL_I 2 "register_operand" "w"))] + (match_operand:SVE_PARTIAL_I 2 "register_operand" "0, w"))] UNSPEC_PRED_X))] "TARGET_SVE && (~ & ) == 0" - "xt\t%0., %1/m, %2." + "@ + xt\t%0., %1/m, %2. + movprfx\t%0, %2\;xt\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated truncate-and-sign-extend operations. (define_insn "@aarch64_pred_sxt" - [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w") + [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w, ?&w") (unspec:SVE_FULL_HSDI - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (sign_extend:SVE_FULL_HSDI (truncate:SVE_PARTIAL_I - (match_operand:SVE_FULL_HSDI 2 "register_operand" "w")))] + (match_operand:SVE_FULL_HSDI 2 "register_operand" "0, w")))] UNSPEC_PRED_X))] "TARGET_SVE && (~ & ) == 0" - "sxt\t%0., %1/m, %2." + "@ + sxt\t%0., %1/m, %2. + movprfx\t%0, %2\;sxt\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated truncate-and-sign-extend operations with merging. @@ -3212,20 +3227,23 @@ ) (define_insn "*cnot" - [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w") + [(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w") (unspec:SVE_FULL_I [(unspec: - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (match_operand:SI 5 "aarch64_sve_ptrue_flag") (eq: - (match_operand:SVE_FULL_I 2 "register_operand" "w") + (match_operand:SVE_FULL_I 2 "register_operand" "0, w") (match_operand:SVE_FULL_I 3 "aarch64_simd_imm_zero"))] UNSPEC_PRED_Z) (match_operand:SVE_FULL_I 4 "aarch64_simd_imm_one") (match_dup 3)] UNSPEC_SEL))] "TARGET_SVE" - "cnot\t%0., %1/m, %2." + "@ + cnot\t%0., %1/m, %2. + movprfx\t%0, %2\;cnot\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated logical inverse with merging. @@ -3383,14 +3401,17 @@ ;; Predicated floating-point unary operations. (define_insn "@aarch64_pred_" - [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w") + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, ?&w") (unspec:SVE_FULL_F - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:SVE_FULL_F 2 "register_operand" "w")] + (match_operand:SVE_FULL_F 2 "register_operand" "0, w")] SVE_COND_FP_UNARY))] "TARGET_SVE" - "\t%0., %1/m, %2." + "@ + \t%0., %1/m, %2. + movprfx\t%0, %2\;\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated floating-point unary arithmetic with merging. @@ -8575,26 +8596,32 @@ ;; Predicated float-to-integer conversion, either to the same width or wider. (define_insn "@aarch64_sve__nontrunc" - [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w") + [(set (match_operand:SVE_FULL_HSDI 0 "register_operand" "=w, ?&w") (unspec:SVE_FULL_HSDI - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:SVE_FULL_F 2 "register_operand" "w")] + (match_operand:SVE_FULL_F 2 "register_operand" "0, w")] SVE_COND_FCVTI))] "TARGET_SVE && >= " - "fcvtz\t%0., %1/m, %2." + "@ + fcvtz\t%0., %1/m, %2. + movprfx\t%0, %2\;fcvtz\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated narrowing float-to-integer conversion. (define_insn "@aarch64_sve__trunc" - [(set (match_operand:VNx4SI_ONLY 0 "register_operand" "=w") + [(set (match_operand:VNx4SI_ONLY 0 "register_operand" "=w, ?&w") (unspec:VNx4SI_ONLY - [(match_operand:VNx2BI 1 "register_operand" "Upl") + [(match_operand:VNx2BI 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:VNx2DF_ONLY 2 "register_operand" "w")] + (match_operand:VNx2DF_ONLY 2 "register_operand" "0, w")] SVE_COND_FCVTI))] "TARGET_SVE" - "fcvtz\t%0., %1/m, %2." + "@ + fcvtz\t%0., %1/m, %2. + movprfx\t%0, %2\;fcvtz\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated float-to-integer conversion with merging, either to the same @@ -8756,26 +8783,32 @@ ;; Predicated integer-to-float conversion, either to the same width or ;; narrower. (define_insn "@aarch64_sve__nonextend" - [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w") + [(set (match_operand:SVE_FULL_F 0 "register_operand" "=w, ?&w") (unspec:SVE_FULL_F - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:SVE_FULL_HSDI 2 "register_operand" "w")] + (match_operand:SVE_FULL_HSDI 2 "register_operand" "0, w")] SVE_COND_ICVTF))] "TARGET_SVE && >= " - "cvtf\t%0., %1/m, %2." + "@ + cvtf\t%0., %1/m, %2. + movprfx\t%0, %2\;cvtf\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated widening integer-to-float conversion. (define_insn "@aarch64_sve__extend" - [(set (match_operand:VNx2DF_ONLY 0 "register_operand" "=w") + [(set (match_operand:VNx2DF_ONLY 0 "register_operand" "=w, ?&w") (unspec:VNx2DF_ONLY - [(match_operand:VNx2BI 1 "register_operand" "Upl") + [(match_operand:VNx2BI 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:VNx4SI_ONLY 2 "register_operand" "w")] + (match_operand:VNx4SI_ONLY 2 "register_operand" "0, w")] SVE_COND_ICVTF))] "TARGET_SVE" - "cvtf\t%0., %1/m, %2." + "@ + cvtf\t%0., %1/m, %2. + movprfx\t%0, %2\;cvtf\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated integer-to-float conversion with merging, either to the same @@ -8948,14 +8981,17 @@ ;; Predicated float-to-float truncation. (define_insn "@aarch64_sve__trunc" - [(set (match_operand:SVE_FULL_HSF 0 "register_operand" "=w") + [(set (match_operand:SVE_FULL_HSF 0 "register_operand" "=w, ?&w") (unspec:SVE_FULL_HSF - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:SVE_FULL_SDF 2 "register_operand" "w")] + (match_operand:SVE_FULL_SDF 2 "register_operand" "0, w")] SVE_COND_FCVT))] "TARGET_SVE && > " - "fcvt\t%0., %1/m, %2." + "@ + fcvt\t%0., %1/m, %2. + movprfx\t%0, %2\;fcvt\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated float-to-float truncation with merging. @@ -9002,14 +9038,17 @@ ;; Predicated BFCVT. (define_insn "@aarch64_sve__trunc" - [(set (match_operand:VNx8BF_ONLY 0 "register_operand" "=w") + [(set (match_operand:VNx8BF_ONLY 0 "register_operand" "=w, ?&w") (unspec:VNx8BF_ONLY - [(match_operand:VNx4BI 1 "register_operand" "Upl") + [(match_operand:VNx4BI 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:VNx4SF_ONLY 2 "register_operand" "w")] + (match_operand:VNx4SF_ONLY 2 "register_operand" "0, w")] SVE_COND_FCVT))] "TARGET_SVE_BF16" - "bfcvt\t%0.h, %1/m, %2.s" + "@ + bfcvt\t%0.h, %1/m, %2.s + movprfx\t%0, %2\;bfcvt\t%0.h, %1/m, %2.s" + [(set_attr "movprfx" "*,yes")] ) ;; Predicated BFCVT with merging. @@ -9099,14 +9138,17 @@ ;; Predicated float-to-float extension. (define_insn "@aarch64_sve__nontrunc" - [(set (match_operand:SVE_FULL_SDF 0 "register_operand" "=w") + [(set (match_operand:SVE_FULL_SDF 0 "register_operand" "=w, ?&w") (unspec:SVE_FULL_SDF - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:SVE_FULL_HSF 2 "register_operand" "w")] + (match_operand:SVE_FULL_HSF 2 "register_operand" "0, w")] SVE_COND_FCVT))] "TARGET_SVE && > " - "fcvt\t%0., %1/m, %2." + "@ + fcvt\t%0., %1/m, %2. + movprfx\t%0, %2\;fcvt\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated float-to-float extension with merging. diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index 12dc9aaac554..772c35079c94 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -1893,10 +1893,10 @@ (unspec:SVE_FULL_SDF [(match_operand: 1 "register_operand" "Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand: 2 "register_operand" "w")] + (match_operand: 2 "register_operand" "0")] SVE2_COND_FP_UNARY_LONG))] "TARGET_SVE2" - "\t%0., %1/m, %2." + "\t%0., %1/m, %0." ) ;; Predicated convert long top with merging. @@ -1978,14 +1978,17 @@ ;; Predicated FCVTX (equivalent to what would be FCVTXNB, except that ;; it supports MOVPRFX). (define_insn "@aarch64_pred_" - [(set (match_operand:VNx4SF_ONLY 0 "register_operand" "=w") + [(set (match_operand:VNx4SF_ONLY 0 "register_operand" "=w, ?&w") (unspec:VNx4SF_ONLY - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand: 2 "register_operand" "w")] + (match_operand: 2 "register_operand" "0, w")] SVE2_COND_FP_UNARY_NARROWB))] "TARGET_SVE2" - "\t%0., %1/m, %2." + "@ + \t%0., %1/m, %2. + movprfx\t%0, %2\;\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated FCVTX with merging. @@ -2076,15 +2079,18 @@ ;; Predicated integer unary operations. (define_insn "@aarch64_pred_" - [(set (match_operand:VNx4SI_ONLY 0 "register_operand" "=w") + [(set (match_operand:VNx4SI_ONLY 0 "register_operand" "=w, ?&w") (unspec:VNx4SI_ONLY - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (unspec:VNx4SI_ONLY - [(match_operand:VNx4SI_ONLY 2 "register_operand" "w")] + [(match_operand:VNx4SI_ONLY 2 "register_operand" "0, w")] SVE2_U32_UNARY)] UNSPEC_PRED_X))] "TARGET_SVE2" - "\t%0., %1/m, %2." + "@ + \t%0., %1/m, %2. + movprfx\t%0, %2\;\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated integer unary operations with merging. @@ -2139,14 +2145,17 @@ ;; Predicated FLOGB. (define_insn "@aarch64_pred_" - [(set (match_operand: 0 "register_operand" "=w") + [(set (match_operand: 0 "register_operand" "=w, ?&w") (unspec: - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl, Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:SVE_FULL_F 2 "register_operand" "w")] + (match_operand:SVE_FULL_F 2 "register_operand" "0, w")] SVE2_COND_INT_UNARY_FP))] "TARGET_SVE2" - "\t%0., %1/m, %2." + "@ + \t%0., %1/m, %2. + movprfx\t%0, %2\;\t%0., %1/m, %2." + [(set_attr "movprfx" "*,yes")] ) ;; Predicated FLOGB with merging. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 67c25878779c..3189dfb90f93 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5390,9 +5390,35 @@ bool aarch64_maybe_expand_sve_subreg_move (rtx dest, rtx src) { gcc_assert (BYTES_BIG_ENDIAN); - if (SUBREG_P (dest)) + + /* Do not try to optimize subregs that LRA has created for matched + reloads. These subregs only exist as a temporary measure to make + the RTL well-formed, but they are exempt from the usual + TARGET_CAN_CHANGE_MODE_CLASS rules. + + For example, if we have: + + (set (reg:VNx8HI R1) (foo:VNx8HI (reg:VNx4SI R2))) + + and the constraints require R1 and R2 to be in the same register, + LRA may need to create RTL such as: + + (set (subreg:VNx4SI (reg:VNx8HI TMP) 0) (reg:VNx4SI R2)) + (set (reg:VNx8HI TMP) (foo:VNx8HI (subreg:VNx4SI (reg:VNx8HI TMP) 0))) + (set (reg:VNx8HI R1) (reg:VNx8HI TMP)) + + which forces both the input and output of the original instruction + to use the same hard register. But for this to work, the normal + rules have to be suppressed on the subreg input, otherwise LRA + would need to reload that input too, meaning that the process + would never terminate. To compensate for this, the normal rules + are also suppressed for the subreg output of the first move. + Ignoring the special case and handling the first move normally + would therefore generate wrong code: we would reverse the elements + for the first subreg but not reverse them back for the second subreg. */ + if (SUBREG_P (dest) && !LRA_SUBREG_P (dest)) dest = SUBREG_REG (dest); - if (SUBREG_P (src)) + if (SUBREG_P (src) && !LRA_SUBREG_P (src)) src = SUBREG_REG (src); /* The optimization handles two single SVE REGs with different element diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f16.c index 2aa8736e645a..09605324cd2a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (abs_f16_x_tied1, svfloat16_t, /* ** abs_f16_x_untied: +** movprfx z0, z1 ** fabs z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f32.c index 30286afc7b7d..797a4187af94 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (abs_f32_x_tied1, svfloat32_t, /* ** abs_f32_x_untied: +** movprfx z0, z1 ** fabs z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f64.c index 28ef9fbba23b..4290ac390d1b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (abs_f64_x_tied1, svfloat64_t, /* ** abs_f64_x_untied: +** movprfx z0, z1 ** fabs z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s16.c index 3b16a9c4f038..fcd5c3413bfd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (abs_s16_x_tied1, svint16_t, /* ** abs_s16_x_untied: +** movprfx z0, z1 ** abs z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s32.c index 14bcbd50c46f..58d183ed9403 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (abs_s32_x_tied1, svint32_t, /* ** abs_s32_x_untied: +** movprfx z0, z1 ** abs z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s64.c index c7b60ff48431..2842048d4eb8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (abs_s64_x_tied1, svint64_t, /* ** abs_s64_x_untied: +** movprfx z0, z1 ** abs z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s8.c index 0bc64c078a26..ec0d89d8ba9c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/abs_s8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (abs_s8_x_tied1, svint8_t, /* ** abs_s8_x_untied: +** movprfx z0, z1 ** abs z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s16.c index 7af312397b94..5f82612c97a1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s16.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cls_s16_z, svuint16_t, svint16_t, /* ** cls_s16_x: +** movprfx z0, z4 ** cls z0\.h, p0/m, z4\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s32.c index 813876f6877f..0db651f2e290 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s32.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cls_s32_z, svuint32_t, svint32_t, /* ** cls_s32_x: +** movprfx z0, z4 ** cls z0\.s, p0/m, z4\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s64.c index 660a20556c80..e809e2fb2ab2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s64.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cls_s64_z, svuint64_t, svint64_t, /* ** cls_s64_x: +** movprfx z0, z4 ** cls z0\.d, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s8.c index 56f5c26086ff..f296c9f932ff 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cls_s8.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cls_s8_z, svuint8_t, svint8_t, /* ** cls_s8_x: +** movprfx z0, z4 ** cls z0\.b, p0/m, z4\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s16.c index 58f89005cd5a..dc2c4e952f75 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s16.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (clz_s16_z, svuint16_t, svint16_t, /* ** clz_s16_x: +** movprfx z0, z4 ** clz z0\.h, p0/m, z4\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s32.c index a9198070b580..17f54bcd0567 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s32.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (clz_s32_z, svuint32_t, svint32_t, /* ** clz_s32_x: +** movprfx z0, z4 ** clz z0\.s, p0/m, z4\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s64.c index 02c0c993e0b7..a42b730c5641 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s64.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (clz_s64_z, svuint64_t, svint64_t, /* ** clz_s64_x: +** movprfx z0, z4 ** clz z0\.d, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s8.c index 642d298c8efc..66c23594f053 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_s8.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (clz_s8_z, svuint8_t, svint8_t, /* ** clz_s8_x: +** movprfx z0, z4 ** clz z0\.b, p0/m, z4\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u16.c index f0872301759b..ab31f567aee6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (clz_u16_x_tied1, svuint16_t, /* ** clz_u16_x_untied: +** movprfx z0, z1 ** clz z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u32.c index e0042413162b..2a7440455a82 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (clz_u32_x_tied1, svuint32_t, /* ** clz_u32_x_untied: +** movprfx z0, z1 ** clz z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u64.c index e879e1b9a6ea..8ff73c424098 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (clz_u64_x_tied1, svuint64_t, /* ** clz_u64_x_untied: +** movprfx z0, z1 ** clz z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u8.c index ce6cb8f45172..89d8c54079c9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/clz_u8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (clz_u8_x_tied1, svuint8_t, /* ** clz_u8_x_untied: +** movprfx z0, z1 ** clz z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s16.c index 19d46be68b57..8f047fbbc0a8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnot_s16_x_tied1, svint16_t, /* ** cnot_s16_x_untied: +** movprfx z0, z1 ** cnot z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s32.c index 041b59a046cc..f5b33959da27 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnot_s32_x_tied1, svint32_t, /* ** cnot_s32_x_untied: +** movprfx z0, z1 ** cnot z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s64.c index c7135cb95689..64121e3f0e18 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnot_s64_x_tied1, svint64_t, /* ** cnot_s64_x_untied: +** movprfx z0, z1 ** cnot z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s8.c index 0560f97516b3..e5dab42ad5ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_s8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnot_s8_x_tied1, svint8_t, /* ** cnot_s8_x_untied: +** movprfx z0, z1 ** cnot z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u16.c index 7ea9ff71ded6..74c72c9ee0f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnot_u16_x_tied1, svuint16_t, /* ** cnot_u16_x_untied: +** movprfx z0, z1 ** cnot z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u32.c index 972c7751eb6b..b0f7531ee087 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnot_u32_x_tied1, svuint32_t, /* ** cnot_u32_x_untied: +** movprfx z0, z1 ** cnot z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u64.c index f25e001c5693..9aa698dfbbf8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnot_u64_x_tied1, svuint64_t, /* ** cnot_u64_x_untied: +** movprfx z0, z1 ** cnot z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u8.c index e135a72956af..67c46a2dd81d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnot_u8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnot_u8_x_tied1, svuint8_t, /* ** cnot_u8_x_untied: +** movprfx z0, z1 ** cnot z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_bf16.c index d92fbc1572d0..bebf36128344 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_bf16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_bf16.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cnt_bf16_z, svuint16_t, svbfloat16_t, /* ** cnt_bf16_x: +** movprfx z0, z4 ** cnt z0\.h, p0/m, z4\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f16.c index b8061bb80dda..20c95d62121a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f16.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cnt_f16_z, svuint16_t, svfloat16_t, /* ** cnt_f16_x: +** movprfx z0, z4 ** cnt z0\.h, p0/m, z4\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f32.c index b9292c97709d..8afeb49da4f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f32.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cnt_f32_z, svuint32_t, svfloat32_t, /* ** cnt_f32_x: +** movprfx z0, z4 ** cnt z0\.s, p0/m, z4\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f64.c index 4976ee467a2a..b7683a97f68e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_f64.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cnt_f64_z, svuint64_t, svfloat64_t, /* ** cnt_f64_x: +** movprfx z0, z4 ** cnt z0\.d, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s16.c index a8ff8f3d2cfb..824c42ad549d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s16.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cnt_s16_z, svuint16_t, svint16_t, /* ** cnt_s16_x: +** movprfx z0, z4 ** cnt z0\.h, p0/m, z4\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s32.c index 3d16041f24e2..d6653d57e00b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s32.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cnt_s32_z, svuint32_t, svint32_t, /* ** cnt_s32_x: +** movprfx z0, z4 ** cnt z0\.s, p0/m, z4\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s64.c index 8c8871ba5934..c28db82dc214 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s64.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cnt_s64_z, svuint64_t, svint64_t, /* ** cnt_s64_x: +** movprfx z0, z4 ** cnt z0\.d, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s8.c index 8d85c8e51496..e741b4c93327 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_s8.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (cnt_s8_z, svuint8_t, svint8_t, /* ** cnt_s8_x: +** movprfx z0, z4 ** cnt z0\.b, p0/m, z4\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u16.c index f173d3108f21..49236cd2cdcd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnt_u16_x_tied1, svuint16_t, /* ** cnt_u16_x_untied: +** movprfx z0, z1 ** cnt z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u32.c index 11969a6b6ed6..d302e323023d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnt_u32_x_tied1, svuint32_t, /* ** cnt_u32_x_untied: +** movprfx z0, z1 ** cnt z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u64.c index 4eb69ea846e1..b6e26ba1725c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnt_u64_x_tied1, svuint64_t, /* ** cnt_u64_x_untied: +** movprfx z0, z1 ** cnt z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u8.c index 30e798302194..464dc4e8c31d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cnt_u8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (cnt_u8_x_tied1, svuint8_t, /* ** cnt_u8_x_untied: +** movprfx z0, z1 ** cnt z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_bf16.c index 52baa1f58817..d4f9150728a8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_bf16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_bf16.c @@ -66,6 +66,7 @@ TEST_DUAL_Z_REV (cvt_bf16_f32_x_tied1, svbfloat16_t, svfloat32_t, /* ** cvt_bf16_f32_x_untied: +** movprfx z0, z4 ** bfcvt z0\.h, p0/m, z4\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f16.c index 5dcd480464bc..dbb042d46dfd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f16.c @@ -421,6 +421,7 @@ TEST_DUAL_Z_REV (cvt_f16_f32_x_tied1, svfloat16_t, svfloat32_t, /* ** cvt_f16_f32_x_untied: +** movprfx z0, z4 ** fcvt z0\.h, p0/m, z4\.s ** ret */ @@ -439,6 +440,7 @@ TEST_DUAL_Z_REV (cvt_f16_f64_x_tied1, svfloat16_t, svfloat64_t, /* ** cvt_f16_f64_x_untied: +** movprfx z0, z4 ** fcvt z0\.h, p0/m, z4\.d ** ret */ @@ -457,6 +459,7 @@ TEST_DUAL_Z_REV (cvt_f16_s16_x_tied1, svfloat16_t, svint16_t, /* ** cvt_f16_s16_x_untied: +** movprfx z0, z4 ** scvtf z0\.h, p0/m, z4\.h ** ret */ @@ -475,6 +478,7 @@ TEST_DUAL_Z_REV (cvt_f16_s32_x_tied1, svfloat16_t, svint32_t, /* ** cvt_f16_s32_x_untied: +** movprfx z0, z4 ** scvtf z0\.h, p0/m, z4\.s ** ret */ @@ -493,6 +497,7 @@ TEST_DUAL_Z_REV (cvt_f16_s64_x_tied1, svfloat16_t, svint64_t, /* ** cvt_f16_s64_x_untied: +** movprfx z0, z4 ** scvtf z0\.h, p0/m, z4\.d ** ret */ @@ -511,6 +516,7 @@ TEST_DUAL_Z_REV (cvt_f16_u16_x_tied1, svfloat16_t, svuint16_t, /* ** cvt_f16_u16_x_untied: +** movprfx z0, z4 ** ucvtf z0\.h, p0/m, z4\.h ** ret */ @@ -529,6 +535,7 @@ TEST_DUAL_Z_REV (cvt_f16_u32_x_tied1, svfloat16_t, svuint32_t, /* ** cvt_f16_u32_x_untied: +** movprfx z0, z4 ** ucvtf z0\.h, p0/m, z4\.s ** ret */ @@ -547,6 +554,7 @@ TEST_DUAL_Z_REV (cvt_f16_u64_x_tied1, svfloat16_t, svuint64_t, /* ** cvt_f16_u64_x_untied: +** movprfx z0, z4 ** ucvtf z0\.h, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f32.c index c1646993996d..f7bfe57ada4c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f32.c @@ -319,6 +319,7 @@ TEST_DUAL_Z_REV (cvt_f32_f16_x_tied1, svfloat32_t, svfloat16_t, /* ** cvt_f32_f16_x_untied: +** movprfx z0, z4 ** fcvt z0\.s, p0/m, z4\.h ** ret */ @@ -337,6 +338,7 @@ TEST_DUAL_Z_REV (cvt_f32_f64_x_tied1, svfloat32_t, svfloat64_t, /* ** cvt_f32_f64_x_untied: +** movprfx z0, z4 ** fcvt z0\.s, p0/m, z4\.d ** ret */ @@ -355,6 +357,7 @@ TEST_DUAL_Z_REV (cvt_f32_s32_x_tied1, svfloat32_t, svint32_t, /* ** cvt_f32_s32_x_untied: +** movprfx z0, z4 ** scvtf z0\.s, p0/m, z4\.s ** ret */ @@ -373,6 +376,7 @@ TEST_DUAL_Z_REV (cvt_f32_s64_x_tied1, svfloat32_t, svint64_t, /* ** cvt_f32_s64_x_untied: +** movprfx z0, z4 ** scvtf z0\.s, p0/m, z4\.d ** ret */ @@ -391,6 +395,7 @@ TEST_DUAL_Z_REV (cvt_f32_u32_x_tied1, svfloat32_t, svuint32_t, /* ** cvt_f32_u32_x_untied: +** movprfx z0, z4 ** ucvtf z0\.s, p0/m, z4\.s ** ret */ @@ -409,6 +414,7 @@ TEST_DUAL_Z_REV (cvt_f32_u64_x_tied1, svfloat32_t, svuint64_t, /* ** cvt_f32_u64_x_untied: +** movprfx z0, z4 ** ucvtf z0\.s, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f64.c index 1d08e6ec503d..bfa36baf2807 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_f64.c @@ -319,6 +319,7 @@ TEST_DUAL_Z_REV (cvt_f64_f16_x_tied1, svfloat64_t, svfloat16_t, /* ** cvt_f64_f16_x_untied: +** movprfx z0, z4 ** fcvt z0\.d, p0/m, z4\.h ** ret */ @@ -337,6 +338,7 @@ TEST_DUAL_Z_REV (cvt_f64_f32_x_tied1, svfloat64_t, svfloat32_t, /* ** cvt_f64_f32_x_untied: +** movprfx z0, z4 ** fcvt z0\.d, p0/m, z4\.s ** ret */ @@ -355,6 +357,7 @@ TEST_DUAL_Z_REV (cvt_f64_s32_x_tied1, svfloat64_t, svint32_t, /* ** cvt_f64_s32_x_untied: +** movprfx z0, z4 ** scvtf z0\.d, p0/m, z4\.s ** ret */ @@ -373,6 +376,7 @@ TEST_DUAL_Z_REV (cvt_f64_s64_x_tied1, svfloat64_t, svint64_t, /* ** cvt_f64_s64_x_untied: +** movprfx z0, z4 ** scvtf z0\.d, p0/m, z4\.d ** ret */ @@ -391,6 +395,7 @@ TEST_DUAL_Z_REV (cvt_f64_u32_x_tied1, svfloat64_t, svuint32_t, /* ** cvt_f64_u32_x_untied: +** movprfx z0, z4 ** ucvtf z0\.d, p0/m, z4\.s ** ret */ @@ -409,6 +414,7 @@ TEST_DUAL_Z_REV (cvt_f64_u64_x_tied1, svfloat64_t, svuint64_t, /* ** cvt_f64_u64_x_untied: +** movprfx z0, z4 ** ucvtf z0\.d, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s16.c index 81761ab092cb..6b6883be8dbf 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s16.c @@ -64,6 +64,7 @@ TEST_DUAL_Z_REV (cvt_s16_f16_x_tied1, svint16_t, svfloat16_t, /* ** cvt_s16_f16_x_untied: +** movprfx z0, z4 ** fcvtzs z0\.h, p0/m, z4\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s32.c index d30da5cc53a1..bf87356d505c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s32.c @@ -166,6 +166,7 @@ TEST_DUAL_Z_REV (cvt_s32_f16_x_tied1, svint32_t, svfloat16_t, /* ** cvt_s32_f16_x_untied: +** movprfx z0, z4 ** fcvtzs z0\.s, p0/m, z4\.h ** ret */ @@ -184,6 +185,7 @@ TEST_DUAL_Z_REV (cvt_s32_f32_x_tied1, svint32_t, svfloat32_t, /* ** cvt_s32_f32_x_untied: +** movprfx z0, z4 ** fcvtzs z0\.s, p0/m, z4\.s ** ret */ @@ -202,6 +204,7 @@ TEST_DUAL_Z_REV (cvt_s32_f64_x_tied1, svint32_t, svfloat64_t, /* ** cvt_s32_f64_x_untied: +** movprfx z0, z4 ** fcvtzs z0\.s, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s64.c index 68cd80784deb..9be3e05386fe 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_s64.c @@ -166,6 +166,7 @@ TEST_DUAL_Z_REV (cvt_s64_f16_x_tied1, svint64_t, svfloat16_t, /* ** cvt_s64_f16_x_untied: +** movprfx z0, z4 ** fcvtzs z0\.d, p0/m, z4\.h ** ret */ @@ -184,6 +185,7 @@ TEST_DUAL_Z_REV (cvt_s64_f32_x_tied1, svint64_t, svfloat32_t, /* ** cvt_s64_f32_x_untied: +** movprfx z0, z4 ** fcvtzs z0\.d, p0/m, z4\.s ** ret */ @@ -202,6 +204,7 @@ TEST_DUAL_Z_REV (cvt_s64_f64_x_tied1, svint64_t, svfloat64_t, /* ** cvt_s64_f64_x_untied: +** movprfx z0, z4 ** fcvtzs z0\.d, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u16.c index 4db0dffdd977..33a608b01fbb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u16.c @@ -64,6 +64,7 @@ TEST_DUAL_Z_REV (cvt_u16_f16_x_tied1, svuint16_t, svfloat16_t, /* ** cvt_u16_f16_x_untied: +** movprfx z0, z4 ** fcvtzu z0\.h, p0/m, z4\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u32.c index 52ef49fcf092..4791d2798fc3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u32.c @@ -166,6 +166,7 @@ TEST_DUAL_Z_REV (cvt_u32_f16_x_tied1, svuint32_t, svfloat16_t, /* ** cvt_u32_f16_x_untied: +** movprfx z0, z4 ** fcvtzu z0\.s, p0/m, z4\.h ** ret */ @@ -184,6 +185,7 @@ TEST_DUAL_Z_REV (cvt_u32_f32_x_tied1, svuint32_t, svfloat32_t, /* ** cvt_u32_f32_x_untied: +** movprfx z0, z4 ** fcvtzu z0\.s, p0/m, z4\.s ** ret */ @@ -202,6 +204,7 @@ TEST_DUAL_Z_REV (cvt_u32_f64_x_tied1, svuint32_t, svfloat64_t, /* ** cvt_u32_f64_x_untied: +** movprfx z0, z4 ** fcvtzu z0\.s, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u64.c index 0c43758aeb44..e6c10c19b658 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_u64.c @@ -166,6 +166,7 @@ TEST_DUAL_Z_REV (cvt_u64_f16_x_tied1, svuint64_t, svfloat16_t, /* ** cvt_u64_f16_x_untied: +** movprfx z0, z4 ** fcvtzu z0\.d, p0/m, z4\.h ** ret */ @@ -184,6 +185,7 @@ TEST_DUAL_Z_REV (cvt_u64_f32_x_tied1, svuint64_t, svfloat32_t, /* ** cvt_u64_f32_x_untied: +** movprfx z0, z4 ** fcvtzu z0\.d, p0/m, z4\.s ** ret */ @@ -202,6 +204,7 @@ TEST_DUAL_Z_REV (cvt_u64_f64_x_tied1, svuint64_t, svfloat64_t, /* ** cvt_u64_f64_x_untied: +** movprfx z0, z4 ** fcvtzu z0\.d, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s16.c index 32e836f013bc..76c71437dc1b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (extb_s16_x_tied1, svint16_t, /* ** extb_s16_x_untied: +** movprfx z0, z1 ** sxtb z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s32.c index e2f13f41cf57..084c1c19b32e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (extb_s32_x_tied1, svint32_t, /* ** extb_s32_x_untied: +** movprfx z0, z1 ** sxtb z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s64.c index 83363efdb7f7..8f3ee8d053bb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extb_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (extb_s64_x_tied1, svint64_t, /* ** extb_s64_x_untied: +** movprfx z0, z1 ** sxtb z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s32.c index 3bb0bf31f206..d15cf7a62cd2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (exth_s32_x_tied1, svint32_t, /* ** exth_s32_x_untied: +** movprfx z0, z1 ** sxth z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s64.c index 0718b67ad149..d8adf52efa20 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/exth_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (exth_s64_x_tied1, svint64_t, /* ** exth_s64_x_untied: +** movprfx z0, z1 ** sxth z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_s64.c index a6edadfa75ca..978a622e09f8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/extw_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (extw_s64_x_tied1, svint64_t, /* ** extw_s64_x_untied: +** movprfx z0, z1 ** sxtw z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f16.c index c31eba922189..c43c6eb7a196 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (neg_f16_x_tied1, svfloat16_t, /* ** neg_f16_x_untied: +** movprfx z0, z1 ** fneg z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f32.c index a57d264ad559..3e9fd5b46f57 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (neg_f32_x_tied1, svfloat32_t, /* ** neg_f32_x_untied: +** movprfx z0, z1 ** fneg z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f64.c index 90cadd4f9694..880f5e8867f6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (neg_f64_x_tied1, svfloat64_t, /* ** neg_f64_x_untied: +** movprfx z0, z1 ** fneg z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s16.c index 80b2ee0f7ac1..6a43bb20c37f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (neg_s16_x_tied1, svint16_t, /* ** neg_s16_x_untied: +** movprfx z0, z1 ** neg z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s32.c index b8805034eb90..ea92412b5f8f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (neg_s32_x_tied1, svint32_t, /* ** neg_s32_x_untied: +** movprfx z0, z1 ** neg z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s64.c index 82abe672350b..911d1f3db16b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (neg_s64_x_tied1, svint64_t, /* ** neg_s64_x_untied: +** movprfx z0, z1 ** neg z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s8.c index b7c9949ad1ea..ace74b747b2d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/neg_s8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (neg_s8_x_tied1, svint8_t, /* ** neg_s8_x_untied: +** movprfx z0, z1 ** neg z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s16.c index bacd6b12cc21..9cafba96ea5a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (not_s16_x_tied1, svint16_t, /* ** not_s16_x_untied: +** movprfx z0, z1 ** not z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s32.c index 8b15d6e91c85..2185b7831251 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (not_s32_x_tied1, svint32_t, /* ** not_s32_x_untied: +** movprfx z0, z1 ** not z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s64.c index 8e7f7b9e876d..09b3c2558527 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (not_s64_x_tied1, svint64_t, /* ** not_s64_x_untied: +** movprfx z0, z1 ** not z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s8.c index e807f08f8109..029909e5cfd8 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_s8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (not_s8_x_tied1, svint8_t, /* ** not_s8_x_untied: +** movprfx z0, z1 ** not z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u16.c index c812005f1181..fc33c99fffb3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (not_u16_x_tied1, svuint16_t, /* ** not_u16_x_untied: +** movprfx z0, z1 ** not z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u32.c index 7b7e9ca2189d..3f5e822ac94f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (not_u32_x_tied1, svuint32_t, /* ** not_u32_x_untied: +** movprfx z0, z1 ** not z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u64.c index 27b92ad84d46..01dde36ec43b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (not_u64_x_tied1, svuint64_t, /* ** not_u64_x_untied: +** movprfx z0, z1 ** not z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u8.c index bd2f36cade80..e8553e3935ca 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/not_u8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (not_u8_x_tied1, svuint8_t, /* ** not_u8_x_untied: +** movprfx z0, z1 ** not z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s16.c index 4f794f60074c..5889c92ff6d1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rbit_s16_x_tied1, svint16_t, /* ** rbit_s16_x_untied: +** movprfx z0, z1 ** rbit z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s32.c index 8b5e1a463a89..1414e3e35ecd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rbit_s32_x_tied1, svint32_t, /* ** rbit_s32_x_untied: +** movprfx z0, z1 ** rbit z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s64.c index cec27a42182a..3b76f5483a02 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rbit_s64_x_tied1, svint64_t, /* ** rbit_s64_x_untied: +** movprfx z0, z1 ** rbit z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s8.c index 9c152116acfc..1fc80e34ce74 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_s8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rbit_s8_x_tied1, svint8_t, /* ** rbit_s8_x_untied: +** movprfx z0, z1 ** rbit z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u16.c index 001ef2bf0756..647933723472 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rbit_u16_x_tied1, svuint16_t, /* ** rbit_u16_x_untied: +** movprfx z0, z1 ** rbit z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u32.c index 4d91e954d7d6..3e959642a334 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rbit_u32_x_tied1, svuint32_t, /* ** rbit_u32_x_untied: +** movprfx z0, z1 ** rbit z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u64.c index 77f88d116a16..5163b82b35c7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rbit_u64_x_tied1, svuint64_t, /* ** rbit_u64_x_untied: +** movprfx z0, z1 ** rbit z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u8.c index fa347e4c7e32..2372398c7e14 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rbit_u8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rbit_u8_x_tied1, svuint8_t, /* ** rbit_u8_x_untied: +** movprfx z0, z1 ** rbit z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f16.c index 2dd7ada2c211..da63f267dd32 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (recpx_f16_x_tied1, svfloat16_t, /* ** recpx_f16_x_untied: +** movprfx z0, z1 ** frecpx z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f32.c index 6364fb83ba32..ea8cb785367b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (recpx_f32_x_tied1, svfloat32_t, /* ** recpx_f32_x_untied: +** movprfx z0, z1 ** frecpx z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f64.c index ca5232331db7..1eaca67a2d23 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/recpx_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (recpx_f64_x_tied1, svfloat64_t, /* ** recpx_f64_x_untied: +** movprfx z0, z1 ** frecpx z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s16.c index ecfabe668eef..a99260f0f30e 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revb_s16_x_tied1, svint16_t, /* ** revb_s16_x_untied: +** movprfx z0, z1 ** revb z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s32.c index a46a819737a8..adbf1286129a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revb_s32_x_tied1, svint32_t, /* ** revb_s32_x_untied: +** movprfx z0, z1 ** revb z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s64.c index 21547238c756..d21db75bf20c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revb_s64_x_tied1, svint64_t, /* ** revb_s64_x_untied: +** movprfx z0, z1 ** revb z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u16.c index d58bd3d74098..d48704f819dd 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revb_u16_x_tied1, svuint16_t, /* ** revb_u16_x_untied: +** movprfx z0, z1 ** revb z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u32.c index 33df990d55f0..cf9293bfb332 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revb_u32_x_tied1, svuint32_t, /* ** revb_u32_x_untied: +** movprfx z0, z1 ** revb z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u64.c index 50ad618cc1a5..54db72dab2f4 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revb_u64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revb_u64_x_tied1, svuint64_t, /* ** revb_u64_x_untied: +** movprfx z0, z1 ** revb z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s32.c index 07d512ddb757..fb63c17d7023 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revh_s32_x_tied1, svint32_t, /* ** revh_s32_x_untied: +** movprfx z0, z1 ** revh z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s64.c index b1446347c0f7..967600ad6236 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revh_s64_x_tied1, svint64_t, /* ** revh_s64_x_untied: +** movprfx z0, z1 ** revh z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u32.c index 9ea51884d1ae..265f865b57f4 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revh_u32_x_tied1, svuint32_t, /* ** revh_u32_x_untied: +** movprfx z0, z1 ** revh z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u64.c index 7b2da2701c0f..733b229b9ecf 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revh_u64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revh_u64_x_tied1, svuint64_t, /* ** revh_u64_x_untied: +** movprfx z0, z1 ** revh z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_s64.c index 26ca0f0bd521..08941314c5a3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revw_s64_x_tied1, svint64_t, /* ** revw_s64_x_untied: +** movprfx z0, z1 ** revw z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_u64.c index c70cdb428bad..ebde929b2c61 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/revw_u64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (revw_u64_x_tied1, svuint64_t, /* ** revw_u64_x_untied: +** movprfx z0, z1 ** revw z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f16.c index 99a604209425..3e1a788045c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rinta_f16_x_tied1, svfloat16_t, /* ** rinta_f16_x_untied: +** movprfx z0, z1 ** frinta z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f32.c index b4e3714bc4e3..ae6fe659cbeb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rinta_f32_x_tied1, svfloat32_t, /* ** rinta_f32_x_untied: +** movprfx z0, z1 ** frinta z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f64.c index 24d6b7dc8b25..2f7be6c46de3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinta_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rinta_f64_x_tied1, svfloat64_t, /* ** rinta_f64_x_untied: +** movprfx z0, z1 ** frinta z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f16.c index 1f0ac85e33a4..ec3b908f9fc1 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rinti_f16_x_tied1, svfloat16_t, /* ** rinti_f16_x_untied: +** movprfx z0, z1 ** frinti z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f32.c index cf54fde5c36a..061f5c8253db 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rinti_f32_x_tied1, svfloat32_t, /* ** rinti_f32_x_untied: +** movprfx z0, z1 ** frinti z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f64.c index 08b861caa1eb..eca3be0816ef 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rinti_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rinti_f64_x_tied1, svfloat64_t, /* ** rinti_f64_x_untied: +** movprfx z0, z1 ** frinti z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f16.c index 194d01cbd0bc..35cb97610d09 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintm_f16_x_tied1, svfloat16_t, /* ** rintm_f16_x_untied: +** movprfx z0, z1 ** frintm z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f32.c index 6c3297aa1a3e..d65baf562c53 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintm_f32_x_tied1, svfloat32_t, /* ** rintm_f32_x_untied: +** movprfx z0, z1 ** frintm z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f64.c index ecbb2444766a..d3824ecd3bd5 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintm_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintm_f64_x_tied1, svfloat64_t, /* ** rintm_f64_x_untied: +** movprfx z0, z1 ** frintm z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f16.c index 273307ef1347..cc2bf0ee281d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintn_f16_x_tied1, svfloat16_t, /* ** rintn_f16_x_untied: +** movprfx z0, z1 ** frintn z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f32.c index bafd43106d1e..aa0c65acdaa6 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintn_f32_x_tied1, svfloat32_t, /* ** rintn_f32_x_untied: +** movprfx z0, z1 ** frintn z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f64.c index 0142315e6957..a9317adec15b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintn_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintn_f64_x_tied1, svfloat64_t, /* ** rintn_f64_x_untied: +** movprfx z0, z1 ** frintn z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f16.c index 0e85c34481ac..f511452e9a72 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintp_f16_x_tied1, svfloat16_t, /* ** rintp_f16_x_untied: +** movprfx z0, z1 ** frintp z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f32.c index cec360d7cce0..34596c4b07f9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintp_f32_x_tied1, svfloat32_t, /* ** rintp_f32_x_untied: +** movprfx z0, z1 ** frintp z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f64.c index 1305fb6823f4..a68a5791bbc9 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintp_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintp_f64_x_tied1, svfloat64_t, /* ** rintp_f64_x_untied: +** movprfx z0, z1 ** frintp z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f16.c index 96f7f2c72065..a86e0630d3a2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintx_f16_x_tied1, svfloat16_t, /* ** rintx_f16_x_untied: +** movprfx z0, z1 ** frintx z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f32.c index 1c42d2a9480e..956515025c3f 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintx_f32_x_tied1, svfloat32_t, /* ** rintx_f32_x_untied: +** movprfx z0, z1 ** frintx z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f64.c index bee806b3bee4..a5c7a01ac773 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintx_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintx_f64_x_tied1, svfloat64_t, /* ** rintx_f64_x_untied: +** movprfx z0, z1 ** frintx z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f16.c index be13d82b4a3e..cb61080db286 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintz_f16_x_tied1, svfloat16_t, /* ** rintz_f16_x_untied: +** movprfx z0, z1 ** frintz z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f32.c index 873c0d468aec..a479909b96e2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintz_f32_x_tied1, svfloat32_t, /* ** rintz_f32_x_untied: +** movprfx z0, z1 ** frintz z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f64.c index e6c9d1fc86f6..f80f9078263a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/rintz_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rintz_f64_x_tied1, svfloat64_t, /* ** rintz_f64_x_untied: +** movprfx z0, z1 ** frintz z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f16.c index 6dc5940fb9b1..335fb86bc9d3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (sqrt_f16_x_tied1, svfloat16_t, /* ** sqrt_f16_x_untied: +** movprfx z0, z1 ** fsqrt z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f32.c index 71d1f8f74e4a..0887996799db 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (sqrt_f32_x_tied1, svfloat32_t, /* ** sqrt_f32_x_untied: +** movprfx z0, z1 ** fsqrt z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f64.c index 7771df545db6..7dbab87919dc 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sqrt_f64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (sqrt_f64_x_tied1, svfloat64_t, /* ** sqrt_f64_x_untied: +** movprfx z0, z1 ** fsqrt z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtlt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtlt_f32.c index 911defafd7a0..f66fa901340c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtlt_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtlt_f32.c @@ -42,7 +42,13 @@ TEST_DUAL_Z_REV (cvtlt_f32_f16_x_tied1, svfloat32_t, svfloat16_t, /* ** cvtlt_f32_f16_x_untied: -** fcvtlt z0\.s, p0/m, z4\.h +** ( +** mov z0\.d, z4\.d +** fcvtlt z0\.s, p0/m, z0\.h +** | +** fcvtlt z4\.s, p0/m, z4\.h +** mov z0\.d, z4\.d +** ) ** ret */ TEST_DUAL_Z (cvtlt_f32_f16_x_untied, svfloat32_t, svfloat16_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtlt_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtlt_f64.c index c34947be2b4b..b262e2533cf7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtlt_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtlt_f64.c @@ -42,7 +42,13 @@ TEST_DUAL_Z_REV (cvtlt_f64_f32_x_tied1, svfloat64_t, svfloat32_t, /* ** cvtlt_f64_f32_x_untied: -** fcvtlt z0\.d, p0/m, z4\.s +** ( +** mov z0\.d, z4\.d +** fcvtlt z0\.d, p0/m, z0\.s +** | +** fcvtlt z4\.d, p0/m, z4\.s +** mov z0\.d, z4\.d +** ) ** ret */ TEST_DUAL_Z (cvtlt_f64_f32_x_untied, svfloat64_t, svfloat32_t, diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtx_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtx_f32.c index 21724c833dca..85fbc7938758 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtx_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/cvtx_f32.c @@ -64,6 +64,7 @@ TEST_DUAL_Z_REV (cvtx_f32_f64_x_tied1, svfloat32_t, svfloat64_t, /* ** cvtx_f32_f64_x_untied: +** movprfx z0, z4 ** fcvtx z0\.s, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f16.c index bc6815690e87..fe65e640facb 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f16.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (logb_f16_z, svint16_t, svfloat16_t, /* ** logb_f16_x: +** movprfx z0, z4 ** flogb z0\.h, p0/m, z4\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f32.c index 35bdcd17b346..847e1b13507d 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f32.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (logb_f32_z, svint32_t, svfloat32_t, /* ** logb_f32_x: +** movprfx z0, z4 ** flogb z0\.s, p0/m, z4\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f64.c index c7c2cb236ea0..4113a37a6120 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/logb_f64.c @@ -33,6 +33,7 @@ TEST_DUAL_Z (logb_f64_z, svint64_t, svfloat64_t, /* ** logb_f64_x: +** movprfx z0, z4 ** flogb z0\.d, p0/m, z4\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s16.c index 07564882a53e..d7acf47c48fa 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (qabs_s16_x_tied1, svint16_t, /* ** qabs_s16_x_untied: +** movprfx z0, z1 ** sqabs z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s32.c index 5341f78f6588..fc35d1043a2a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (qabs_s32_x_tied1, svint32_t, /* ** qabs_s32_x_untied: +** movprfx z0, z1 ** sqabs z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s64.c index 3679e659e89e..b572785c965b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (qabs_s64_x_tied1, svint64_t, /* ** qabs_s64_x_untied: +** movprfx z0, z1 ** sqabs z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s8.c index dca25f9f1dbe..48b85605e15a 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qabs_s8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (qabs_s8_x_tied1, svint8_t, /* ** qabs_s8_x_untied: +** movprfx z0, z1 ** sqabs z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s16.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s16.c index ca78f9df0428..d8b6c87ed7c2 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s16.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s16.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (qneg_s16_x_tied1, svint16_t, /* ** qneg_s16_x_untied: +** movprfx z0, z1 ** sqneg z0\.h, p0/m, z1\.h ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s32.c index 3d2ed8777403..2342504f4d92 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (qneg_s32_x_tied1, svint32_t, /* ** qneg_s32_x_untied: +** movprfx z0, z1 ** sqneg z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s64.c index e1379863d1f9..61ccb981fce3 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s64.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (qneg_s64_x_tied1, svint64_t, /* ** qneg_s64_x_untied: +** movprfx z0, z1 ** sqneg z0\.d, p0/m, z1\.d ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s8.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s8.c index 13c60efffa90..c7ec6116bb64 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s8.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qneg_s8.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (qneg_s8_x_tied1, svint8_t, /* ** qneg_s8_x_untied: +** movprfx z0, z1 ** sqneg z0\.b, p0/m, z1\.b ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpe_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpe_u32.c index 17c6a72c37f1..c484cec63daf 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpe_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/recpe_u32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (recpe_u32_x_tied1, svuint32_t, /* ** recpe_u32_x_untied: +** movprfx z0, z1 ** urecpe z0\.s, p0/m, z1\.s ** ret */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rsqrte_u32.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rsqrte_u32.c index e9e4fb7dcade..082a810722ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rsqrte_u32.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/rsqrte_u32.c @@ -73,6 +73,7 @@ TEST_UNIFORM_Z (rsqrte_u32_x_tied1, svuint32_t, /* ** rsqrte_u32_x_untied: +** movprfx z0, z1 ** ursqrte z0\.s, p0/m, z1\.s ** ret */