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i386: Enable AVX512 memory broadcast for INT andnot

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Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for INT andnot operations.

gcc/

	PR target/72782
	* config/i386/sse.md (*andnot<mode>3_bcst): New.

gcc/testsuite/

	PR target/72782
	* gcc.target/i386/avx512f-andn-di-zmm-1.c: New test.
	* gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise.
	* gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise.
	* gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise.
	* gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise.
	* gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise.
	* gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise.
	* gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise.

From-SVN: r265370
This commit is contained in:
H.J. Lu 2018-10-22 07:35:48 +00:00 committed by H.J. Lu
parent 0844e4324e
commit a48be73bab
11 changed files with 126 additions and 0 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2018-10-22 H.J. Lu <hongjiu.lu@intel.com>
PR target/72782
* config/i386/sse.md (*andnot<mode>3_bcst): New.
2018-10-22 H.J. Lu <hongjiu.lu@intel.com>
PR target/72782

13
gcc/config/i386/sse.md
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@ -12102,6 +12102,19 @@
]
(const_string "<sseinsnmode>")))])
(define_insn "*andnot<mode>3_bcst"
[(set (match_operand:VI 0 "register_operand" "=v")
(and:VI
(not:VI48_AVX512VL
(match_operand:VI48_AVX512VL 1 "register_operand" "v"))
(vec_duplicate:VI48_AVX512VL
(match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
"TARGET_AVX512F"
"vpandn<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
[(set_attr "type" "sselog")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_insn "*andnot<mode>3_mask"
[(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI48_AVX512VL

12
gcc/testsuite/ChangeLog
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@ -1,3 +1,15 @@
2018-10-22 H.J. Lu <hongjiu.lu@intel.com>
PR target/72782
* gcc.target/i386/avx512f-andn-di-zmm-1.c: New test.
* gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise.
2018-10-22 H.J. Lu <hongjiu.lu@intel.com>
PR target/72782

12
gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vpandnq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
#define type __m512i
#define vec 512
#define op andnot
#define suffix epi64
#define SCALAR long long
#include "avx512-binop-1.h"

12
gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
#define type __m512i
#define vec 512
#define op andnot
#define suffix epi32
#define SCALAR int
#include "avx512-binop-1.h"

12
gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
#define type __m512i
#define vec 512
#define op andnot
#define suffix epi32
#define SCALAR int
#include "avx512-binop-2.h"

12
gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
#define type __m512i
#define vec 512
#define op andnot
#define suffix epi32
#define SCALAR int
#include "avx512-binop-3.h"

12
gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
#define type __m512i
#define vec 512
#define op andnot
#define suffix epi32
#define SCALAR int
#include "avx512-binop-4.h"

12
gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-mavx512f -O2" } */
/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
#define type __m512i
#define vec 512
#define op andnot
#define suffix epi32
#define SCALAR int
#include "avx512-binop-5.h"

12
gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-mavx512vl -O2" } */
/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
#include <immintrin.h>
__m128i
foo (__m128i x, int *f)
{
return (__m128i) (~(__v4su) x & (__v4su) _mm_set1_epi32 (*f));
}

12
gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c Normal file
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@ -0,0 +1,12 @@
/* { dg-do compile } */
/* { dg-options "-mavx512vl -O2" } */
/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
#include <immintrin.h>
__m256i
foo (__m256i x, int *f)
{
return (__m256i) (~(__v8su) x & (__v8su) _mm256_set1_epi32 (*f));
}