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Misc mips16 bug fixes found by gcc/gdb testsuites.
* mips.c (function_prologue): When TARGET_MIPS16, adjust the register offset in the .mask pseudo to compensate for frame pointer adjustments. (mips16_fp_args, build_mips16_call_stub): For little endian, do not word swap arguments moved to/from FP registers. * mips16.S (DFREVCMP): Reverse arguments to OPCODE. From-SVN: r23586
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@ -1,3 +1,11 @@
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Mon Nov 9 16:37:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* mips.c (function_prologue): When TARGET_MIPS16, adjust the register
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offset in the .mask pseudo to compensate for frame pointer adjustments.
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(mips16_fp_args, build_mips16_call_stub): For little endian, do not
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word swap arguments moved to/from FP registers.
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* mips16.S (DFREVCMP): Reverse arguments to OPCODE.
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Mon Nov 9 09:47:06 PST 1998 Jeff Law (law@cygnus.com)
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* version.c: Bump for snapshot.
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@ -6085,7 +6085,10 @@ function_prologue (file, size)
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fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
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current_frame_info.mask,
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current_frame_info.gp_save_offset,
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((frame_pointer_needed && TARGET_MIPS16)
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? (current_frame_info.gp_save_offset
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- current_function_outgoing_args_size)
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: current_frame_info.gp_save_offset),
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current_frame_info.fmask,
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current_frame_info.fp_save_offset);
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}
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@ -7434,9 +7437,14 @@ mips16_fp_args (file, fp_code, from_fp_p)
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{
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if ((fparg & 1) != 0)
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++fparg;
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fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
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reg_names[gparg], reg_names[fparg + 1], s,
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reg_names[gparg + 1], reg_names[fparg]);
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if (TARGET_BIG_ENDIAN)
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fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
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reg_names[gparg], reg_names[fparg + 1], s,
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reg_names[gparg + 1], reg_names[fparg]);
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else
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fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
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reg_names[gparg], reg_names[fparg], s,
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reg_names[gparg + 1], reg_names[fparg + 1]);
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++gparg;
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++fparg;
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}
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@ -7777,12 +7785,24 @@ build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
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reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
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else
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{
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[GP_REG_FIRST + 2],
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reg_names[FP_REG_FIRST + 1]);
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[GP_REG_FIRST + 3],
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reg_names[FP_REG_FIRST + 0]);
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if (TARGET_BIG_ENDIAN)
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{
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[GP_REG_FIRST + 2],
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reg_names[FP_REG_FIRST + 1]);
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[GP_REG_FIRST + 3],
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reg_names[FP_REG_FIRST + 0]);
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}
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else
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{
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[GP_REG_FIRST + 2],
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reg_names[FP_REG_FIRST + 0]);
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fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
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reg_names[GP_REG_FIRST + 3],
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reg_names[FP_REG_FIRST + 1]);
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}
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}
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fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
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/* As above, we can't fill the delay slot. */
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@ -330,7 +330,7 @@ STARTFN (NAME); \
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STARTFN (NAME); \
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LDDBL1; \
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LDDBL2; \
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OPCODE $f12,$f14; \
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OPCODE $f14,$f12; \
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li $2,TRUE; \
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bc1t 1f; \
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li $2,FALSE; \
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