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[aarch64] Fold ldr+dup to ld1rq for little endian targets.

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gcc/ChangeLog:
	* config/aarch64/aarch64-sve.md (aarch64_vec_duplicate_vq<mode>_le):
	Change to define_insn_and_split to fold ldr+dup to ld1rq.
	* config/aarch64/predicates.md (aarch64_sve_dup_ld1rq_operand): New.

gcc/testsuite/ChangeLog:
	* gcc.target/aarch64/sve/acle/general/pr96463-2.c: Adjust.
This commit is contained in:
Prathamesh Kulkarni 2023-01-14 23:21:55 +05:30
parent 9afc914809
commit a3b99b8460
3 changed files with 31 additions and 6 deletions
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26
gcc/config/aarch64/aarch64-sve.md
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@ -2533,14 +2533,34 @@
)
;; Duplicate an Advanced SIMD vector to fill an SVE vector (LE version).
(define_insn "@aarch64_vec_duplicate_vq<mode>_le"
[(set (match_operand:SVE_FULL 0 "register_operand" "=w")
(define_insn_and_split "@aarch64_vec_duplicate_vq<mode>_le"
[(set (match_operand:SVE_FULL 0 "register_operand" "=w, w")
(vec_duplicate:SVE_FULL
(match_operand:<V128> 1 "register_operand" "w")))]
(match_operand:<V128> 1 "aarch64_sve_dup_ld1rq_operand" "w, UtQ")))
(clobber (match_scratch:VNx16BI 2 "=X, Upl"))]
"TARGET_SVE && !BYTES_BIG_ENDIAN"
{
switch (which_alternative)
{
case 0:
operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
return "dup\t%0.q, %1.q[0]";
case 1:
return "#";
default:
gcc_unreachable ();
}
}
"&& MEM_P (operands[1])"
[(const_int 0)]
{
if (GET_CODE (operands[2]) == SCRATCH)
operands[2] = gen_reg_rtx (VNx16BImode);
emit_move_insn (operands[2], CONSTM1_RTX (VNx16BImode));
rtx gp = gen_lowpart (<VPRED>mode, operands[2]);
emit_insn (gen_aarch64_sve_ld1rq<mode> (operands[0], operands[1], gp));
DONE;
}
)

4
gcc/config/aarch64/predicates.md
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@ -676,6 +676,10 @@
(ior (match_operand 0 "register_operand")
(match_operand 0 "aarch64_sve_ld1r_operand")))
(define_predicate "aarch64_sve_dup_ld1rq_operand"
(ior (match_operand 0 "register_operand")
(match_operand 0 "aarch64_sve_ld1rq_operand")))
(define_predicate "aarch64_sve_ptrue_svpattern_immediate"
(and (match_code "const")
(match_test "aarch64_sve_ptrue_svpattern_p (op, NULL)")))

3
gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr96463-2.c
View File

@ -26,4 +26,5 @@ TEST(svfloat64_t, float64_t, f64)
TEST(svbfloat16_t, bfloat16_t, bf16)
/* { dg-final { scan-assembler-times {\tdup\tz[0-9]+\.q, z[0-9]+\.q\[0\]} 12 { target aarch64_little_endian } } } */
/* { dg-final { scan-assembler-not {\tdup\t} } } */
/* { dg-final { scan-assembler-times {\tld1rq} 12 } } */