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RISC-V: Libitm add RISC-V support.
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file.
This commit is contained in:
Xiongchuan Tan
Jeff Law
parent
db55f1dda2
commit
a3b58f28b8
63
libitm/config/riscv/asm.h
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63
libitm/config/riscv/asm.h
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@ -0,0 +1,63 @@
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/* Copyright (C) 2022 Free Software Foundation, Inc.
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Contributed by Xiongchuan Tan <xc-tan@outlook.com>.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#ifndef _RV_ASM_H
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#define _RV_ASM_H
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#ifdef __riscv_e
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# error "rv32e and rv64e unsupported"
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#endif
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#if __riscv_xlen == 64
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# define GPR_L ld
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# define GPR_S sd
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# define SZ_GPR 8
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# define LEN_GPR 14
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#elif __riscv_xlen == 32
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# define GPR_L lw
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# define GPR_S sw
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# define SZ_GPR 4
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# define LEN_GPR 16 /* Extra padding to align the stack to 16 bytes */
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#else
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# error Unsupported XLEN (must be 64-bit or 32-bit).
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#endif
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#if defined(__riscv_flen) && __riscv_flen == 64
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# define FPR_L fld
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# define FPR_S fsd
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# define SZ_FPR 8
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#elif defined(__riscv_flen) && __riscv_flen == 32
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# define FPR_L flw
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# define FPR_S fsw
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# define SZ_FPR 4
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#elif defined(__riscv_flen)
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# error Q-extension unsupported
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#else
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# define SZ_FPR 0
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#endif
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/* The size of gtm_jmpbuf */
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#define ADJ_STACK_SIZE (LEN_GPR*SZ_GPR+12*SZ_FPR)
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#endif /* _RV_ASM_H */
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144
libitm/config/riscv/sjlj.S
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144
libitm/config/riscv/sjlj.S
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@ -0,0 +1,144 @@
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/* Copyright (C) 2022 Free Software Foundation, Inc.
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Contributed by Xiongchuan Tan <xc-tan@outlook.com>.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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#include "asmcfi.h"
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#include "asm.h"
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.text
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.align 2
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.global _ITM_beginTransaction
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.type _ITM_beginTransaction, @function
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_ITM_beginTransaction:
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cfi_startproc
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mv a1, sp
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addi sp, sp, -ADJ_STACK_SIZE
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cfi_adjust_cfa_offset(ADJ_STACK_SIZE)
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/* Return Address */
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GPR_S ra, 0*SZ_GPR(sp)
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cfi_rel_offset(ra, 0*SZ_GPR)
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/* Caller's sp */
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GPR_S a1, 1*SZ_GPR(sp)
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/* Caller's s0/fp */
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GPR_S fp, 2*SZ_GPR(sp)
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cfi_rel_offset(fp, 2*SZ_GPR)
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/* Callee-saved registers */
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GPR_S s1, 3*SZ_GPR(sp)
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GPR_S s2, 4*SZ_GPR(sp)
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GPR_S s3, 5*SZ_GPR(sp)
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GPR_S s4, 6*SZ_GPR(sp)
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GPR_S s5, 7*SZ_GPR(sp)
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GPR_S s6, 8*SZ_GPR(sp)
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GPR_S s7, 9*SZ_GPR(sp)
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GPR_S s8, 10*SZ_GPR(sp)
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GPR_S s9, 11*SZ_GPR(sp)
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GPR_S s10, 12*SZ_GPR(sp)
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GPR_S s11, 13*SZ_GPR(sp)
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#if defined(__riscv_flen)
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/* Callee-saved floating-point registers */
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FPR_S fs0, 0*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs1, 1*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs2, 2*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs3, 3*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs4, 4*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs5, 5*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs6, 6*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs7, 7*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs8, 8*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs9, 9*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs10, 10*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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FPR_S fs11, 11*SZ_FPR+LEN_GPR*SZ_GPR(sp)
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#endif
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mv fp, sp
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/* Invoke GTM_begin_transaction with the struct we've just built. */
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mv a1, sp
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jal ra, GTM_begin_transaction
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/* Return; we don't need to restore any of the call-saved regs. */
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GPR_L ra, 0*SZ_GPR(sp)
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cfi_restore(ra)
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GPR_L fp, 2*SZ_GPR(sp)
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cfi_restore(fp)
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addi sp, sp, ADJ_STACK_SIZE
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cfi_adjust_cfa_offset(-ADJ_STACK_SIZE)
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ret
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cfi_endproc
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.size _ITM_beginTransaction, . - _ITM_beginTransaction
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.align 2
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.global GTM_longjmp
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.hidden GTM_longjmp
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.type GTM_longjmp, @function
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GTM_longjmp:
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/* The first parameter becomes the return value (a0).
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The third parameter is ignored for now. */
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cfi_startproc
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GPR_L s1, 3*SZ_GPR(a1)
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GPR_L s2, 4*SZ_GPR(a1)
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GPR_L s3, 5*SZ_GPR(a1)
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GPR_L s4, 6*SZ_GPR(a1)
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GPR_L s5, 7*SZ_GPR(a1)
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GPR_L s6, 8*SZ_GPR(a1)
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GPR_L s7, 9*SZ_GPR(a1)
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GPR_L s8, 10*SZ_GPR(a1)
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GPR_L s9, 11*SZ_GPR(a1)
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GPR_L s10, 12*SZ_GPR(a1)
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GPR_L s11, 13*SZ_GPR(a1)
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#if defined(__riscv_flen)
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FPR_L fs0, 0*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs1, 1*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs2, 2*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs3, 3*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs4, 4*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs5, 5*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs6, 6*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs7, 7*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs8, 8*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs9, 9*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs10, 10*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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FPR_L fs11, 11*SZ_FPR+LEN_GPR*SZ_GPR(a1)
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#endif
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GPR_L ra, 0*SZ_GPR(a1)
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GPR_L fp, 2*SZ_GPR(a1)
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GPR_L a3, 1*SZ_GPR(a1)
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cfi_def_cfa(a1, 0)
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mv sp, a3
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jr ra
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cfi_endproc
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.size GTM_longjmp, . - GTM_longjmp
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#ifdef __linux__
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.section .note.GNU-stack, "", @progbits
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#endif
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64
libitm/config/riscv/target.h
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64
libitm/config/riscv/target.h
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@ -0,0 +1,64 @@
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/* Copyright (C) 2022 Free Software Foundation, Inc.
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Contributed by Xiongchuan Tan <xc-tan@outlook.com>.
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This file is part of the GNU Transactional Memory Library (libitm).
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Libitm is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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more details.
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Under Section 7 of GPL version 3, you are granted additional
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permissions described in the GCC Runtime Library Exception, version
|
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3.1, as published by the Free Software Foundation.
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You should have received a copy of the GNU General Public License and
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a copy of the GCC Runtime Library Exception along with this program;
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see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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<http://www.gnu.org/licenses/>. */
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namespace GTM HIDDEN {
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typedef struct gtm_jmpbuf
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{
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long int pc;
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void *cfa;
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long int s[12]; /* Saved registers, s0 is fp */
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#if __riscv_xlen == 32
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/* Ensure that the stack is 16-byte aligned */
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long int padding[2];
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#endif
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/* FP saved registers */
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#if defined(__riscv_flen) && __riscv_flen == 64
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double fs[12];
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#elif defined(__riscv_flen) && __riscv_flen == 32
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float fs[12];
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#elif defined(__riscv_flen)
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# error Q-extension unsupported
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#endif
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} gtm_jmpbuf;
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/* The size of one line in hardware caches (in bytes). */
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/* 64 bytes is a suggested value in the RVA profiles (see
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https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc). */
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#define HW_CACHELINE_SIZE 64
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static inline void
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cpu_relax (void)
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{
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#ifdef __riscv_zihintpause
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__asm volatile ("pause");
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#else
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/* Encoding of the pause instruction */
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__asm volatile (".4byte 0x100000F");
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#endif
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}
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} // namespace GTM
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@ -82,6 +82,8 @@ EOF
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loongarch*) ARCH=loongarch ;;
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riscv*) ARCH=riscv ;;
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sh*) ARCH=sh ;;
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sparc)
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