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re PR other/29972 (typos in the manual)
PR other/29972 * doc/invoke.texi (C++ Dialect Options, Optimize Options) (HPPA Options, i386 and x86-64 Options, IA-64 Options) (RS/6000 and PowerPC Options): Fix typos and markup. * doc/passes.texi (Tree-SSA passes): Likewise. From-SVN: r132087
This commit is contained in:
Ralf Wildenhues
Gerald Pfeifer
parent
91f385f8cd
commit
a31cfd58cf
@ -1,3 +1,11 @@
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2008-02-04 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
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PR other/29972
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* doc/invoke.texi (C++ Dialect Options, Optimize Options)
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(HPPA Options, i386 and x86-64 Options, IA-64 Options)
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(RS/6000 and PowerPC Options): Fix typos and markup.
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* doc/passes.texi (Tree-SSA passes): Likewise.
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2008-02-02 Michael Matz <matz@suse.de>
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PR target/35045
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@ -1782,7 +1782,7 @@ functions for use by the C++ runtime type identification features
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of the language, you can save some space by using this flag. Note that
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exception handling uses the same information, but it will generate it as
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needed. The @samp{dynamic_cast} operator can still be used for casts that
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do not require runtime type information, i.e. casts to @code{void *} or to
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do not require runtime type information, i.e.@: casts to @code{void *} or to
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unambiguous base classes.
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@item -fstats
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@ -6764,7 +6764,7 @@ units larger than this limit is limited by @option{--param inline-unit-growth}.
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For small units this might be too tight (consider unit consisting of function A
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that is inline and B that just calls A three time. If B is small relative to
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A, the growth of unit is 300\% and yet such inlining is very sane. For very
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large units consisting of small inlininable functions however the overall unit
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large units consisting of small inlineable functions however the overall unit
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growth limit is needed to avoid exponential explosion of code size. Thus for
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smaller units, the size is increased to @option{--param large-unit-insns}
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before applying @option{--param inline-unit-growth}. The default is 10000
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@ -7125,7 +7125,7 @@ is 10000.
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@item integer-share-limit
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Small integer constants can use a shared data structure, reducing the
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compiler's memory usage and increasing its speed. This sets the maximum
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value of a shared integer constant's. The default value is 256.
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value of a shared integer constant. The default value is 256.
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@item min-virtual-mappings
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Specifies the minimum number of virtual mappings in the incremental
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@ -7140,7 +7140,7 @@ SSA updater switches to a full update for those symbols. The default
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ratio is 3.
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@item ssp-buffer-size
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The minimum size of buffers (i.e. arrays) that will receive stack smashing
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The minimum size of buffers (i.e.@: arrays) that will receive stack smashing
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protection when @option{-fstack-protection} is used.
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@item max-jump-thread-duplication-stmts
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@ -10107,7 +10107,7 @@ are passed to that ld. The ld that is called is determined by the
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@option{--with-ld} configure option, GCC's program search path, and
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finally by the user's @env{PATH}. The linker used by GCC can be printed
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using @samp{which `gcc -print-prog-name=ld`}. This option is only available
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on the 64 bit HP-UX GCC, i.e. configured with @samp{hppa*64*-*-hpux*}.
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on the 64 bit HP-UX GCC, i.e.@: configured with @samp{hppa*64*-*-hpux*}.
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@item -mhp-ld
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@opindex hp-ld
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@ -10120,7 +10120,7 @@ ld. The ld that is called is determined by the @option{--with-ld}
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configure option, GCC's program search path, and finally by the user's
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@env{PATH}. The linker used by GCC can be printed using @samp{which
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`gcc -print-prog-name=ld`}. This option is only available on the 64 bit
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HP-UX GCC, i.e. configured with @samp{hppa*64*-*-hpux*}.
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HP-UX GCC, i.e.@: configured with @samp{hppa*64*-*-hpux*}.
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@item -mlong-calls
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@opindex mno-long-calls
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@ -10277,16 +10277,16 @@ instruction set support.
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@item k6
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AMD K6 CPU with MMX instruction set support.
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@item k6-2, k6-3
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Improved versions of AMD K6 CPU with MMX and 3dNOW! instruction set support.
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Improved versions of AMD K6 CPU with MMX and 3dNOW!@: instruction set support.
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@item athlon, athlon-tbird
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AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and SSE prefetch instructions
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AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and SSE prefetch instructions
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support.
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@item athlon-4, athlon-xp, athlon-mp
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Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and full SSE
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Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and full SSE
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instruction set support.
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@item k8, opteron, athlon64, athlon-fx
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AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
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MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
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MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW!@: and 64-bit instruction set extensions.)
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@item k8-sse3, opteron-sse3, athlon64-sse3
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Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
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@item amdfam10, barcelona
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@ -10297,10 +10297,10 @@ instruction set extensions.)
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IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
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set support.
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@item winchip2
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IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!
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IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!@:
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instruction set support.
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@item c3
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Via C3 CPU with MMX and 3dNOW! instruction set support. (No scheduling is
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Via C3 CPU with MMX and 3dNOW!@: instruction set support. (No scheduling is
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implemented for this chip.)
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@item c3-2
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Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is
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@ -10614,7 +10614,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
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@opindex m3dnow
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@opindex mno-3dnow
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These switches enable or disable the use of instructions in the MMX,
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SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4A, SSE5, ABM or 3DNow! extended
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SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4A, SSE5, ABM or 3DNow!@: extended
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instruction sets.
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These extensions are also available as built-in functions: see
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@ref{X86 Built-in Functions}, for details of the functions enabled and
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@ -10973,7 +10973,7 @@ The default is 'enable'.
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@opindex mno-sched-control-spec
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@opindex msched-control-spec
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(Dis/En)able control speculative scheduling. This feature is
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available only during region scheduling (i.e. before reload).
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available only during region scheduling (i.e.@: before reload).
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This will result in generation of the ld.s instructions and
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the corresponding check instructions chk.s .
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The default is 'disable'.
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@ -13291,7 +13291,7 @@ will set or clear the bit.
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@opindex msim
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On embedded PowerPC systems, assume that the startup module is called
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@file{sim-crt0.o} and that the standard C libraries are @file{libsim.a} and
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@file{libc.a}. This is the default for @samp{powerpc-*-eabisim}.
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@file{libc.a}. This is the default for @samp{powerpc-*-eabisim}
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configurations.
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@item -mmvme
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@ -490,7 +490,7 @@ described by @code{pass_vrp}.
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@item Folding built-in functions
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This pass simplifies built-in functions, as applicable, with constant
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arguments or with inferrable string lengths. It is located in
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arguments or with inferable string lengths. It is located in
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@file{tree-ssa-ccp.c} and is described by @code{pass_fold_builtins}.
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@item Split critical edges
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