mirror/gcc
2
0
Fork 0
mirror of git://gcc.gnu.org/git/gcc.git synced 2025-01-13 21:05:30 +08:00
Code Issues Packages Projects Releases Wiki Activity

rs6000.md (extenddftf2): Change to define_insn which copies first FPR and clears second.

Browse Source 
* config/rs6000/rs6000.md (extenddftf2): Change to define_insn
        which copies first FPR and clears second.
        (extendsftf2): Same.
        (floatditf2): Fix typo.
        (floatsitf2): Same.
        (fix_trunctfdi2): Same.
        (fix_trunctfsi2): Same.

From-SVN: r57990
This commit is contained in:
David Edelsohn 2002-10-09 20:54:05 +00:00 committed by David Edelsohn
parent fb7e6024db
commit a2419b9670
2 changed files with 45 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2002-10-09 David Edelsohn <edelsohn@gnu.org>
* config/rs6000/rs6000.md (extenddftf2): Change to define_insn
which copies first FPR and clears second.
(extendsftf2): Same.
(floatditf2): Fix typo.
(floatsitf2): Same.
(fix_trunctfdi2): Same.
(fix_trunctfsi2): Same.
2002-10-09 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> 2002-10-09 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
* conflict.c (arc_hash): Change return type to hashval_t. * conflict.c (arc_hash): Change return type to hashval_t.

68
gcc/config/rs6000/rs6000.md
View File

@ -8516,8 +8516,8 @@
operands[2] = gen_lowpart (DImode, operands[0]); operands[2] = gen_lowpart (DImode, operands[0]);
/* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
#if HOST_BITS_PER_WIDE_INT >= 64 #if HOST_BITS_PER_WIDE_INT >= 64
val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
operands[3] = gen_int_mode (val, DImode); operands[3] = gen_int_mode (val, DImode);
#else #else
@ -8797,12 +8797,12 @@
operands[2] = gen_lowpart (DImode, operands[0]); operands[2] = gen_lowpart (DImode, operands[0]);
operands[3] = gen_highpart (DImode, operands[0]); operands[3] = gen_highpart (DImode, operands[0]);
#if HOST_BITS_PER_WIDE_INT >= 64 #if HOST_BITS_PER_WIDE_INT >= 64
val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32 | val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32
((HOST_WIDE_INT)(unsigned long)l[1])); | ((HOST_WIDE_INT)(unsigned long)l[1]));
operands[4] = gen_int_mode (val, DImode); operands[4] = gen_int_mode (val, DImode);
val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32 | val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32
((HOST_WIDE_INT)(unsigned long)l[3])); | ((HOST_WIDE_INT)(unsigned long)l[3]));
operands[5] = gen_int_mode (val, DImode); operands[5] = gen_int_mode (val, DImode);
#else #else
operands[4] = immed_double_const (l[1], l[0], DImode); operands[4] = immed_double_const (l[1], l[0], DImode);
@ -8810,33 +8810,33 @@
#endif #endif
}") }")
(define_insn_and_split "extenddftf2" (define_insn "extenddftf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f") [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
(float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))] (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_LONG_DOUBLE_128" && TARGET_LONG_DOUBLE_128"
"#" "*
""
[(set (match_dup 2) (match_dup 3))]
"
{ {
operands[2] = gen_rtx_REG (DFmode, REGNO (operands[0] + 1)); if (REGNO (operands[0]) == REGNO (operands[1]))
operands[3] = CONST0_RTX (DFmode); return \"fsub %L0,%L0,%L0\";
}") else
return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
}"
[(set_attr "type" "fp")])
(define_insn_and_split "extendsftf2" (define_insn "extendsftf2"
[(set (match_operand:TF 0 "gpc_reg_operand" "=f") [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
(float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))] (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_LONG_DOUBLE_128" && TARGET_LONG_DOUBLE_128"
"#" "*
""
[(set (match_dup 2) (match_dup 3))]
"
{ {
operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0] + 1)); if (REGNO (operands[0]) == REGNO (operands[1]))
operands[3] = CONST0_RTX (SFmode); return \"fsub %L0,%L0,%L0\";
}") else
return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
}"
[(set_attr "type" "fp")])
(define_insn "trunctfdf2" (define_insn "trunctfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f") [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
@ -8870,8 +8870,8 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(float:DF (match_operand:DI 1 "gpc_reg_operand" ""))) (float:DF (match_dup 1)))
(set (match_operand:TF 0 "gpc_reg_operand" "") (set (match_dup 0)
(float_extend:TF (match_dup 2)))] (float_extend:TF (match_dup 2)))]
"") "")
@ -8884,34 +8884,36 @@
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) (float:DF (match_dup 1)))
(set (match_operand:TF 0 "gpc_reg_operand" "") (set (match_dup 0)
(float_extend:TF (match_dup 2)))] (float_extend:TF (match_dup 2)))]
"") "")
(define_insn_and_split "fix_trunctfdi2" (define_insn_and_split "fix_trunctfdi2"
[(set (match_operand:DI 0 "gpc_reg_operand" "=*f") [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
(fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))] (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))
(clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) (float_truncate:DF (match_dup 1)))
(set (match_operand:DI 0 "gpc_reg_operand" "") (set (match_dup 0)
(fix:SI (match_dup 2)))] (fix:DI (match_dup 2)))]
"") "")
(define_insn_and_split "fix_trunctfsi2" (define_insn_and_split "fix_trunctfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r") [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))] (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
(clobber (match_scratch:DF 2 "=f"))]
"DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
&& TARGET_LONG_DOUBLE_128" && TARGET_LONG_DOUBLE_128"
"#" "#"
"&& reload_completed" "&& reload_completed"
[(set (match_dup 2) [(set (match_dup 2)
(float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) (float_truncate:DF (match_dup 1)))
(set (match_operand:SI 0 "gpc_reg_operand" "") (set (match_dup 0)
(fix:SI (match_dup 2)))] (fix:SI (match_dup 2)))]
"") "")