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i386: Fix some -mavx512vl -mno-avx512bw bugs [PR99321]
As I wrote in the mail with the previous PR99321 fix, we have various bugs where we emit instructions that need avx512bw and avx512vl ISAs when compiling with -mavx512vl -mno-avx512bw. Without the following patch, the attached testcase fails with: /tmp/ccW4PsfG.s: Assembler messages: /tmp/ccW4PsfG.s:9: Error: unsupported instruction `vpaddb' /tmp/ccW4PsfG.s:20: Error: unsupported instruction `vpaddb' /tmp/ccW4PsfG.s:31: Error: unsupported instruction `vpaddw' /tmp/ccW4PsfG.s:42: Error: unsupported instruction `vpaddw' /tmp/ccW4PsfG.s:53: Error: unsupported instruction `vpsubb' /tmp/ccW4PsfG.s:64: Error: unsupported instruction `vpsubb' /tmp/ccW4PsfG.s:75: Error: unsupported instruction `vpsubw' /tmp/ccW4PsfG.s:86: Error: unsupported instruction `vpsubw' /tmp/ccW4PsfG.s:97: Error: unsupported instruction `vpmullw' /tmp/ccW4PsfG.s:108: Error: unsupported instruction `vpmullw' /tmp/ccW4PsfG.s:133: Error: unsupported instruction `vpminub' /tmp/ccW4PsfG.s:144: Error: unsupported instruction `vpminuw' /tmp/ccW4PsfG.s:155: Error: unsupported instruction `vpminuw' /tmp/ccW4PsfG.s:166: Error: unsupported instruction `vpminsb' /tmp/ccW4PsfG.s:177: Error: unsupported instruction `vpminsb' /tmp/ccW4PsfG.s:202: Error: unsupported instruction `vpminsw' /tmp/ccW4PsfG.s:227: Error: unsupported instruction `vpmaxub' /tmp/ccW4PsfG.s:238: Error: unsupported instruction `vpmaxuw' /tmp/ccW4PsfG.s:249: Error: unsupported instruction `vpmaxuw' /tmp/ccW4PsfG.s:260: Error: unsupported instruction `vpmaxsb' /tmp/ccW4PsfG.s:271: Error: unsupported instruction `vpmaxsb' /tmp/ccW4PsfG.s:296: Error: unsupported instruction `vpmaxsw' We already have Yw constraint which is equivalent to v for -mavx512bw -mavx512vl and to nothing otherwise, per discussions this patch changes it to stand for x otherwise. As it is an undocumented internal constraint, hopefully it won't affect any inline asm in the wild. For the instructions that need both we need to use Yw and v for modes that don't need that. 2021-03-07 Jakub Jelinek <jakub@redhat.com> PR target/99321 * config/i386/constraints.md (Yw): Use SSE_REGS if TARGET_SSE but TARGET_AVX512BW or TARGET_AVX512VL is not set. Adjust description and comment. * config/i386/sse.md (v_Yw): New define_mode_attr. (*<insn><mode>3, *mul<mode>3<mask_name>, *avx2_<code><mode>3, *sse4_1_<code><mode>3<mask_name>): Use <v_Yw> instead of v in constraints. * config/i386/mmx.md (mmx_pshufw_1, *vec_dupv4hi): Use Yw instead of xYw in constraints. * lib/target-supports.exp (check_effective_target_assembler_march_noavx512bw): New effective target. * gcc.target/i386/avx512vl-pr99321-1.c: New test.
This commit is contained in:
Jakub Jelinek
parent
0ad6a2e2f0
commit
a18ebd6c43
gcc
config/i386
testsuite
@ -110,7 +110,7 @@
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;; v any EVEX encodable SSE register for AVX512VL target,
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;; otherwise any SSE register
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;; w any EVEX encodable SSE register for AVX512BW with TARGET_AVX512VL
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;; target.
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;; target, otherwise any SSE register.
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(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
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"First SSE register (@code{%xmm0}).")
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@ -148,8 +148,8 @@
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"@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
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(define_register_constraint "Yw"
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"TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : NO_REGS"
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"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target.")
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"TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
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"@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target, otherwise any SSE register.")
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;; We use the B prefix to denote any number of internal operands:
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;; f FLAGS_REG
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@ -2021,9 +2021,9 @@
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})
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(define_insn "mmx_pshufw_1"
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[(set (match_operand:V4HI 0 "register_operand" "=y,xYw")
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[(set (match_operand:V4HI 0 "register_operand" "=y,Yw")
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(vec_select:V4HI
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(match_operand:V4HI 1 "register_mmxmem_operand" "ym,xYw")
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(match_operand:V4HI 1 "register_mmxmem_operand" "ym,Yw")
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(parallel [(match_operand 2 "const_0_to_3_operand")
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(match_operand 3 "const_0_to_3_operand")
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(match_operand 4 "const_0_to_3_operand")
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@ -2105,10 +2105,10 @@
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(set_attr "mode" "DI,TI")])
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(define_insn "*vec_dupv4hi"
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[(set (match_operand:V4HI 0 "register_operand" "=y,xYw")
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[(set (match_operand:V4HI 0 "register_operand" "=y,Yw")
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(vec_duplicate:V4HI
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(truncate:HI
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(match_operand:SI 1 "register_operand" "0,xYw"))))]
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(match_operand:SI 1 "register_operand" "0,Yw"))))]
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"(TARGET_MMX || TARGET_MMX_WITH_SSE)
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&& (TARGET_SSE || TARGET_3DNOW_A)"
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"@
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@ -560,6 +560,14 @@
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(V4SF "avx512vl") (V8SF "avx512vl") (V16SF "avx512f")
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(V2DF "avx512vl") (V4DF "avx512vl") (V8DF "avx512f")])
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(define_mode_attr v_Yw
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[(V16QI "Yw") (V32QI "Yw") (V64QI "v")
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(V8HI "Yw") (V16HI "Yw") (V32HI "v")
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(V4SI "v") (V8SI "v") (V16SI "v")
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(V2DI "v") (V4DI "v") (V8DI "v")
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(V4SF "v") (V8SF "v") (V16SF "v")
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(V2DF "v") (V4DF "v") (V8DF "v")])
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(define_mode_attr sse2_avx_avx512f
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[(V16QI "sse2") (V32QI "avx") (V64QI "avx512f")
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(V8HI "avx512vl") (V16HI "avx512vl") (V32HI "avx512bw")
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@ -11677,10 +11685,10 @@
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"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
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(define_insn "*<insn><mode>3"
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[(set (match_operand:VI_AVX2 0 "register_operand" "=x,v")
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[(set (match_operand:VI_AVX2 0 "register_operand" "=x,<v_Yw>")
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(plusminus:VI_AVX2
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(match_operand:VI_AVX2 1 "bcst_vector_operand" "<comm>0,v")
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(match_operand:VI_AVX2 2 "bcst_vector_operand" "xBm,vmBr")))]
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(match_operand:VI_AVX2 1 "bcst_vector_operand" "<comm>0,<v_Yw>")
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(match_operand:VI_AVX2 2 "bcst_vector_operand" "xBm,<v_Yw>mBr")))]
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"TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
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"@
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p<plusminus_mnemonic><ssemodesuffix>\t{%2, %0|%0, %2}
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@ -11790,9 +11798,9 @@
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"ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
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(define_insn "*mul<mode>3<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
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(mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,v")
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(match_operand:VI2_AVX2 2 "vector_operand" "xBm,vm")))]
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,<v_Yw>")
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(mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "vector_operand" "%0,<v_Yw>")
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(match_operand:VI2_AVX2 2 "vector_operand" "xBm,<v_Yw>m")))]
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"TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))
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&& <mask_mode512bit_condition> && <mask_avx512bw_condition>"
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"@
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@ -12618,10 +12626,10 @@
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"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
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(define_insn "*avx2_<code><mode>3"
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[(set (match_operand:VI124_256 0 "register_operand" "=v")
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[(set (match_operand:VI124_256 0 "register_operand" "=<v_Yw>")
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(maxmin:VI124_256
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(match_operand:VI124_256 1 "nonimmediate_operand" "%v")
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(match_operand:VI124_256 2 "nonimmediate_operand" "vm")))]
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(match_operand:VI124_256 1 "nonimmediate_operand" "%<v_Yw>")
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(match_operand:VI124_256 2 "nonimmediate_operand" "<v_Yw>m")))]
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"TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
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"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
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[(set_attr "type" "sseiadd")
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@ -12745,10 +12753,10 @@
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})
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(define_insn "*sse4_1_<code><mode>3<mask_name>"
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[(set (match_operand:VI14_128 0 "register_operand" "=Yr,*x,v")
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[(set (match_operand:VI14_128 0 "register_operand" "=Yr,*x,<v_Yw>")
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(smaxmin:VI14_128
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(match_operand:VI14_128 1 "vector_operand" "%0,0,v")
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(match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,vm")))]
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(match_operand:VI14_128 1 "vector_operand" "%0,0,<v_Yw>")
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(match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,<v_Yw>m")))]
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"TARGET_SSE4_1
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&& <mask_mode512bit_condition>
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&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
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@ -12830,10 +12838,10 @@
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})
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(define_insn "*sse4_1_<code><mode>3<mask_name>"
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[(set (match_operand:VI24_128 0 "register_operand" "=Yr,*x,v")
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[(set (match_operand:VI24_128 0 "register_operand" "=Yr,*x,<v_Yw>")
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(umaxmin:VI24_128
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(match_operand:VI24_128 1 "vector_operand" "%0,0,v")
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(match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,vm")))]
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(match_operand:VI24_128 1 "vector_operand" "%0,0,<v_Yw>")
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(match_operand:VI24_128 2 "vector_operand" "YrBm,*xBm,<v_Yw>m")))]
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"TARGET_SSE4_1
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&& <mask_mode512bit_condition>
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&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
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39
gcc/testsuite/gcc.target/i386/avx512vl-pr99321-1.c
Normal file
39
gcc/testsuite/gcc.target/i386/avx512vl-pr99321-1.c
Normal file
@ -0,0 +1,39 @@
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/* PR target/99321 */
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/* { dg-do assemble { target lp64 } } */
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/* { dg-require-effective-target avx512vl } */
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/* { dg-require-effective-target assembler_march_noavx512bw } */
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/* { dg-options "-O2 -mavx512vl -mno-avx512bw -Wa,-march=+noavx512bw" } */
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#include <x86intrin.h>
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typedef unsigned char V1 __attribute__((vector_size (16)));
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typedef unsigned char V2 __attribute__((vector_size (32)));
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typedef unsigned short V3 __attribute__((vector_size (16)));
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typedef unsigned short V4 __attribute__((vector_size (32)));
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void f1 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a += b; __asm ("" : : "v" (a)); }
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void f2 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a += b; __asm ("" : : "v" (a)); }
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void f3 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a += b; __asm ("" : : "v" (a)); }
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void f4 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a += b; __asm ("" : : "v" (a)); }
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void f5 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a -= b; __asm ("" : : "v" (a)); }
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void f6 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a -= b; __asm ("" : : "v" (a)); }
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void f7 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a -= b; __asm ("" : : "v" (a)); }
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void f8 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a -= b; __asm ("" : : "v" (a)); }
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void f9 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a *= b; __asm ("" : : "v" (a)); }
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void f10 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a *= b; __asm ("" : : "v" (a)); }
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void f11 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_min_epu8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); }
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void f12 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_min_epu8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); }
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void f13 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_min_epu16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); }
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void f14 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_min_epu16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); }
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void f15 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_min_epi8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); }
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void f16 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_min_epi8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); }
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void f17 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_min_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); }
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void f18 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_min_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); }
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void f19 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_max_epu8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); }
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void f20 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_max_epu8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); }
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void f21 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_max_epu16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); }
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void f22 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_max_epu16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); }
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void f23 (void) { register V1 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V1) _mm_max_epi8 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); }
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void f24 (void) { register V2 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V2) _mm256_max_epi8 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); }
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void f25 (void) { register V3 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V3) _mm_max_epi16 ((__m128i) a, (__m128i) b); __asm ("" : : "v" (a)); }
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void f26 (void) { register V4 a __asm ("%xmm16"), b __asm ("%xmm17"); __asm ("" : "=v" (a), "=v" (b)); a = (V4) _mm256_max_epi16 ((__m256i) a, (__m256i) b); __asm ("" : : "v" (a)); }
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@ -8945,6 +8945,16 @@ proc check_effective_target_avx512bw { } {
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} "-mavx512bw" ]
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}
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# Return 1 if -Wa,-march=+noavx512bw is supported.
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proc check_effective_target_assembler_march_noavx512bw {} {
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if { [istarget i?86*-*-*] || [istarget x86_64*-*-*] } {
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return [check_no_compiler_messages assembler_march_noavx512bw object {
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void foo (void) {}
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} "-mno-avx512bw -Wa,-march=+noavx512bw"]
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}
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return 0
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}
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# Return 1 if avx512vp2intersect instructions can be compiled.
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proc check_effective_target_avx512vp2intersect { } {
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return [check_no_compiler_messages avx512vp2intersect object {
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