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2064.md ("z_o2", "z_o3"): Remove.
* config/s390/2064.md ("z_o2", "z_o3"): Remove.
* config/s390/2084.md ("x_o2", "x_o3"): Remove.
("x_fdivd"): Use also for fsqrtd type.
("x_fdivs"): Use also for fsqrts type.
* config/s390/s390.md (attribute "type"): Remove "o2" and "o3" types.
("fix_truncdfsi2_ieee"): Set type to "ftoi".
("fix_truncdfsi2_ibm"): Set type to "other".
("floatdidf2", "floatdisf2"): Do not clobber CC.
("floatsidf2", "floatsidf2_ieee"): Likewise.
("floatsisf2", "floatsisf2_ieee"): Likewise.
("truncdfsf2", "truncdfsf2_ieee"): Only allow "register_operand".
("truncdfsf2_ibm"): Only allow "nonimmediate_operand". Use LER
instead of LRER.
("extendsfdf2_ibm"): Do not set atype. Set type to "floads".
("sqrtdf2"): Set type to "fsqrtd".
("sqrtsf2"): Set type to "fsqrts".
From-SVN: r90174
This commit is contained in:
Ulrich Weigand
Ulrich Weigand
parent
b2c24c1b9f
commit
a036c6f739
@ -1,3 +1,22 @@
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2004-11-06 Ulrich Weigand <uweigand@de.ibm.com>
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* config/s390/2064.md ("z_o2", "z_o3"): Remove.
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* config/s390/2084.md ("x_o2", "x_o3"): Remove.
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("x_fdivd"): Use also for fsqrtd type.
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("x_fdivs"): Use also for fsqrts type.
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* config/s390/s390.md (attribute "type"): Remove "o2" and "o3" types.
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("fix_truncdfsi2_ieee"): Set type to "ftoi".
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("fix_truncdfsi2_ibm"): Set type to "other".
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("floatdidf2", "floatdisf2"): Do not clobber CC.
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("floatsidf2", "floatsidf2_ieee"): Likewise.
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("floatsisf2", "floatsisf2_ieee"): Likewise.
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("truncdfsf2", "truncdfsf2_ieee"): Only allow "register_operand".
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("truncdfsf2_ibm"): Only allow "nonimmediate_operand". Use LER
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instead of LRER.
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("extendsfdf2_ibm"): Do not set atype. Set type to "floads".
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("sqrtdf2"): Set type to "fsqrtd".
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("sqrtsf2"): Set type to "fsqrts".
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2004-11-06 Kazu Hirata <kazu@cs.umass.edu>
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* tree-phinodes.c (remove_all_phi_nodes_for): Speed up using a
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@ -72,16 +72,6 @@
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(eq_attr "type" "jsr"))
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"z_e1*5,z_wr")
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(define_insn_reservation "z_o2" 2
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(and (eq_attr "cpu" "z900,g5,g6")
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(eq_attr "type" "o2"))
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"z_e1*2,z_wr")
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(define_insn_reservation "z_o3" 3
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(and (eq_attr "cpu" "z900,g5,g6")
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(eq_attr "type" "o3"))
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"z_e1*3,z_wr")
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;
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; Insn still not mentioned are check for
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; the usage of the agen unit
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@ -1,5 +1,5 @@
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;; Scheduling description for z990 (cpu 2084).
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;; Copyright (C) 2003 Free Software Foundation, Inc.
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;; Copyright (C) 2003,2004 Free Software Foundation, Inc.
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;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
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;; Ulrich Weigand (uweigand@de.ibm.com).
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@ -120,16 +120,6 @@
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(eq_attr "op_type" "NN"))
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"x-e1-np,x-wr-np")
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(define_insn_reservation "x_o2" 2
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "o2"))
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"x-e1-np*2,x-wr-np")
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(define_insn_reservation "x_o3" 3
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "o3"))
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"x-e1-np*3,x-wr-np")
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;;
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;; Floating point insns
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;;
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@ -146,12 +136,12 @@
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(define_insn_reservation "x_fdivd" 36
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fdivd"))
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(eq_attr "type" "fdivd,fsqrtd"))
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"x_e1_t*30,x-wr-fp")
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(define_insn_reservation "x_fdivs" 36
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(and (eq_attr "cpu" "z990")
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(eq_attr "type" "fdivs"))
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(eq_attr "type" "fdivs,fsqrts"))
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"x_e1_t*30,x-wr-fp")
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(define_insn_reservation "x_floadd" 6
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@ -160,7 +160,7 @@
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floadd,floads,fstored, fstores,
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fmuld,fmuls,fdivd,fdivs,
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ftoi,itof,fsqrtd,fsqrts,
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other,o2,o3"
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other"
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(const_string "integer"))
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;; Operand type. Used to default length attribute values
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@ -2967,7 +2967,7 @@
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"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
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"cfdbr\t%0,%h2,%1"
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[(set_attr "op_type" "RRE")
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(set_attr "type" "other" )])
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(set_attr "type" "ftoi")])
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(define_insn "fix_truncdfsi2_ibm"
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[(set (match_operand:SI 0 "register_operand" "=d")
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@ -2985,7 +2985,7 @@
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return "l\t%0,%N4";
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}
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[(set_attr "op_type" "NN")
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(set_attr "type" "ftoi")
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(set_attr "type" "other")
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(set_attr "atype" "agen")
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(set_attr "length" "20")])
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@ -3107,8 +3107,7 @@
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(define_insn "floatdidf2"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(float:DF (match_operand:DI 1 "register_operand" "d")))
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(clobber (reg:CC 33))]
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(float:DF (match_operand:DI 1 "register_operand" "d")))]
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"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
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"cdgbr\t%0,%1"
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[(set_attr "op_type" "RRE")
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@ -3120,8 +3119,7 @@
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(define_insn "floatdisf2"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(float:SF (match_operand:DI 1 "register_operand" "d")))
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(clobber (reg:CC 33))]
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(float:SF (match_operand:DI 1 "register_operand" "d")))]
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"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
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"cegbr\t%0,%1"
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[(set_attr "op_type" "RRE")
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@ -3132,10 +3130,8 @@
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;
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(define_expand "floatsidf2"
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[(parallel
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[(set (match_operand:DF 0 "register_operand" "")
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(float:DF (match_operand:SI 1 "register_operand" "")))
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(clobber (reg:CC 33))])]
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[(set (match_operand:DF 0 "register_operand" "")
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(float:DF (match_operand:SI 1 "register_operand" "")))]
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"TARGET_HARD_FLOAT"
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{
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if (TARGET_IBM_FLOAT)
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@ -3152,8 +3148,7 @@
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(define_insn "floatsidf2_ieee"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(float:DF (match_operand:SI 1 "register_operand" "d")))
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(clobber (reg:CC 33))]
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(float:DF (match_operand:SI 1 "register_operand" "d")))]
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"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
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"cdfbr\t%0,%1"
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[(set_attr "op_type" "RRE")
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@ -3183,10 +3178,8 @@
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;
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(define_expand "floatsisf2"
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[(parallel
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[(set (match_operand:SF 0 "register_operand" "")
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(float:SF (match_operand:SI 1 "register_operand" "")))
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(clobber (reg:CC 33))])]
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[(set (match_operand:SF 0 "register_operand" "")
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(float:SF (match_operand:SI 1 "register_operand" "")))]
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"TARGET_HARD_FLOAT"
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{
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if (TARGET_IBM_FLOAT)
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@ -3201,8 +3194,7 @@
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(define_insn "floatsisf2_ieee"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(float:SF (match_operand:SI 1 "register_operand" "d")))
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(clobber (reg:CC 33))]
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(float:SF (match_operand:SI 1 "register_operand" "d")))]
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"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
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"cefbr\t%0,%1"
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[(set_attr "op_type" "RRE")
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@ -3214,23 +3206,23 @@
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(define_expand "truncdfsf2"
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[(set (match_operand:SF 0 "register_operand" "")
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(float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
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(float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
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"TARGET_HARD_FLOAT"
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"")
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(define_insn "truncdfsf2_ieee"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
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(float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
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"ledbr\t%0,%1"
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[(set_attr "op_type" "RRE")])
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(define_insn "truncdfsf2_ibm"
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[(set (match_operand:SF 0 "register_operand" "=f,f")
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(float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
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(float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
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"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
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"@
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lrer\t%0,%1
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ler\t%0,%1
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le\t%0,%1"
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[(set_attr "op_type" "RR,RX")
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(set_attr "type" "floads,floads")])
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@ -3270,9 +3262,8 @@
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sdr\t%0,%0\;ler\t%0,%1
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sdr\t%0,%0\;le\t%0,%1"
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[(set_attr "op_type" "NN,NN")
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(set_attr "atype" "reg,agen")
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(set_attr "length" "4,6")
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(set_attr "type" "o2,o2")])
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(set_attr "type" "floads,floads")])
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;;
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@ -6357,7 +6348,8 @@
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"@
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sqdbr\t%0,%1
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sqdb\t%0,%1"
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[(set_attr "op_type" "RRE,RXE")])
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[(set_attr "op_type" "RRE,RXE")
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(set_attr "type" "fsqrtd")])
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;
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; sqrtsf2 instruction pattern(s).
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@ -6370,7 +6362,8 @@
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"@
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sqebr\t%0,%1
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sqeb\t%0,%1"
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[(set_attr "op_type" "RRE,RXE")])
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[(set_attr "op_type" "RRE,RXE")
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(set_attr "type" "fsqrts")])
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;;
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;;- One complement instructions.
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