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Fix peepholes to prevent pre-/post- increment addressing from clobbering the
source/destination register. From-SVN: r34848
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@ -1,3 +1,9 @@
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2000-07-03 Nick Clifton <nickc@cygnus.com>
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* config/arm/arm.md: Fix post increment and pre increment
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peepholes so that they do not generate UNPREDICATBLE opcodes.
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(ie ones where the increment clobbers the source/destination).
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2000-07-01 Marek Michalkiewicz <marekm@linux.org.pl>
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* config/avr/avr.c (out_adj_frame_ptr): Make "frame pointer
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@ -7701,15 +7701,20 @@
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; It doesn't seem worth adding peepholes for anything but the most common
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; cases since, unlike combine, the increment must immediately follow the load
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; for this pattern to match.
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; When loading we must watch to see that the base register isn't trampled by
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; the load. In such cases this isn't a post-inc expression.
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; We must watch to see that the source/destination register isn't also the
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; same as the base address register, and that if the index is a register,
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; that it is not the same as the base address register. In such cases the
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; instruction that we would generate would have UNPREDICTABLE behaviour so
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; we cannot use it.
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(define_peephole
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[(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r"))
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(match_operand:QI 2 "s_register_operand" "r"))
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(set (match_dup 0)
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(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
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"TARGET_ARM"
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"TARGET_ARM
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&& (REGNO (operands[2]) != REGNO (operands[0]))
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&& (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
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"str%?b\\t%2, [%0], %1")
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(define_peephole
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@ -7717,9 +7722,9 @@
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(mem:QI (match_operand:SI 1 "s_register_operand" "+r")))
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(set (match_dup 1)
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(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
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"TARGET_ARM && REGNO(operands[0]) != REGNO(operands[1])
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&& (GET_CODE (operands[2]) != REG
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|| REGNO(operands[0]) != REGNO (operands[2]))"
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"TARGET_ARM
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&& REGNO (operands[0]) != REGNO(operands[1])
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&& (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))"
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"ldr%?b\\t%0, [%1], %2")
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(define_peephole
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@ -7727,7 +7732,9 @@
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(match_operand:SI 2 "s_register_operand" "r"))
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(set (match_dup 0)
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(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
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"TARGET_ARM"
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"TARGET_ARM
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&& (REGNO (operands[2]) != REGNO (operands[0]))
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&& (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
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"str%?\\t%2, [%0], %1")
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(define_peephole
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@ -7738,9 +7745,8 @@
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"TARGET_ARM
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&& (! BYTES_BIG_ENDIAN)
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&& ! TARGET_MMU_TRAPS
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&& REGNO(operands[0]) != REGNO(operands[1])
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&& (GET_CODE (operands[2]) != REG
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|| REGNO(operands[0]) != REGNO (operands[2]))"
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&& REGNO (operands[0]) != REGNO(operands[1])
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&& (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))"
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"ldr%?\\t%0, [%1], %2\\t%@ loadhi")
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(define_peephole
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@ -7749,9 +7755,8 @@
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(set (match_dup 1)
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(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
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"TARGET_ARM
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&& REGNO(operands[0]) != REGNO(operands[1])
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&& (GET_CODE (operands[2]) != REG
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|| REGNO(operands[0]) != REGNO (operands[2]))"
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&& REGNO (operands[0]) != REGNO(operands[1])
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&& (GET_CODE (operands[2]) != REG || REGNO(operands[0]) != REGNO (operands[2]))"
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"ldr%?\\t%0, [%1], %2")
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(define_peephole
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@ -7759,7 +7764,9 @@
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(match_operand:SI 1 "index_operand" "rJ")))
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(match_operand:QI 2 "s_register_operand" "r"))
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(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
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"TARGET_ARM"
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"TARGET_ARM
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&& (REGNO (operands[2]) != REGNO (operands[0]))
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&& (GET_CODE (operands[1]) != REG || (REGNO (operands[1]) != REGNO (operands[0])))"
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"str%?b\\t%2, [%0, %1]!")
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(define_peephole
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@ -7770,7 +7777,9 @@
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(match_operand:QI 3 "s_register_operand" "r"))
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(set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)])
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(match_dup 2)))]
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"TARGET_ARM"
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"TARGET_ARM
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&& (REGNO (operands[3]) != REGNO (operands[2]))
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&& (REGNO (operands[0]) != REGNO (operands[2]))"
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"str%?b\\t%3, [%2, %0%S4]!")
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; This pattern is never tried by combine, so do it as a peephole
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