diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7717db986087..68b64142d0d3 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2008-11-22  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* config/mips/mips.md (rdhwr): Rename to rdhwr_synci_step_<mode>.
+	Use constant 1 as the operand.
+	* config/mips/mips.c (mips_expand_synci_loop): Make INC Pmode.
+	Rename gen_rdhwr to gen_rdhwr_synci_step_si or
+	gen_rdhwr_synci_step_di depending on the size of Pmode.
+
 2008-11-22  Uros Bizjak  <ubizjak@gmail.com>
 
 	PR target/38222
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index c868b10a1073..c7b3c064b8f6 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -6401,8 +6401,10 @@ mips_expand_synci_loop (rtx begin, rtx end)
   rtx inc, label, cmp, cmp_result;
 
   /* Load INC with the cache line size (rdhwr INC,$1).  */
-  inc = gen_reg_rtx (SImode);
-  emit_insn (gen_rdhwr (inc, const1_rtx));
+  inc = gen_reg_rtx (Pmode);
+  emit_insn (Pmode == SImode
+	     ? gen_rdhwr_synci_step_si (inc)
+	     : gen_rdhwr_synci_step_di (inc));
 
   /* Loop back to here.  */
   label = gen_label_rtx ();
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 22fcc8875cb5..046f6a793a82 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4725,12 +4725,12 @@
   "ISA_HAS_SYNCI"
   "synci\t0(%0)")
 
-(define_insn "rdhwr"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (unspec_volatile [(match_operand:SI 1 "const_int_operand" "n")]
+(define_insn "rdhwr_synci_step_<mode>"
+  [(set (match_operand:P 0 "register_operand" "=d")
+        (unspec_volatile [(const_int 1)]
         UNSPEC_RDHWR))]
   "ISA_HAS_SYNCI"
-  "rdhwr\t%0,$%1")
+  "rdhwr\t%0,$1")
 
 (define_insn "clear_hazard"
   [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)